master
1/*-
2 * SPDX-License-Identifier: BSD-3-Clause
3 *
4 * Copyright (c) 1991 The Regents of the University of California.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of the University nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91
32 */
33
34#ifndef _MACHINE_SPECIALREG_H_
35#define _MACHINE_SPECIALREG_H_
36
37/*
38 * Bits in 386 special registers:
39 */
40#define CR0_PE 0x00000001 /* Protected mode Enable */
41#define CR0_MP 0x00000002 /* "Math" (fpu) Present */
42#define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */
43#define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */
44#define CR0_PG 0x80000000 /* PaGing enable */
45
46/*
47 * Bits in 486 special registers:
48 */
49#define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */
50#define CR0_WP 0x00010000 /* Write Protect (honor page protect in
51 all modes) */
52#define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */
53#define CR0_NW 0x20000000 /* Not Write-through */
54#define CR0_CD 0x40000000 /* Cache Disable */
55
56#define CR3_PCID_MASK 0x0000000000000fff
57#define CR3_LAM_U57 0x2000000000000000
58#define CR3_LAM_U48 0x4000000000000000
59#define CR3_PCID_SAVE 0x8000000000000000
60
61/*
62 * Bits in PPro special registers
63 */
64#define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */
65#define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */
66#define CR4_TSD 0x00000004 /* Time stamp disable */
67#define CR4_DE 0x00000008 /* Debugging extensions */
68#define CR4_PSE 0x00000010 /* Page size extensions */
69#define CR4_PAE 0x00000020 /* Physical address extension */
70#define CR4_MCE 0x00000040 /* Machine check enable */
71#define CR4_PGE 0x00000080 /* Page global enable */
72#define CR4_PCE 0x00000100 /* Performance monitoring counter
73 enable */
74#define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */
75#define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */
76#define CR4_UMIP 0x00000800 /* User Mode Instruction Prevention */
77#define CR4_LA57 0x00001000 /* Enable 5-level paging */
78#define CR4_VMXE 0x00002000 /* enable VMX operation
79 (Intel-specific) */
80#define CR4_FSGSBASE 0x00010000 /* Enable FS/GS BASE access
81 instructions */
82#define CR4_PCIDE 0x00020000 /* Enable Context ID */
83#define CR4_XSAVE 0x00040000 /* XSETBV/XGETBV */
84#define CR4_SMEP 0x00100000 /* Supervisor-Mode Execution
85 Prevention */
86#define CR4_SMAP 0x00200000 /* Supervisor-Mode Access
87 Prevention */
88#define CR4_PKE 0x00400000 /* Protection Keys Enable */
89#define CR4_CET 0x00800000 /* Control-flow Enforcement
90 Technology */
91#define CR4_PKS 0x01000000 /* Protection Keys for Supervisor */
92#define CR4_UINTR 0x02000000 /* User Interrupts Enable */
93#define CR4_LASS 0x08000000 /* Linear Address Space Separation */
94#define CR4_LAM_SUP 0x10000000 /* Linear-Address Masking for
95 Supervisor */
96
97/*
98 * Bits in AMD64 special registers. EFER is 64 bits wide.
99 */
100#define EFER_SCE 0x000000001 /* System Call Extensions (R/W) */
101#define EFER_LME 0x000000100 /* Long mode enable (R/W) */
102#define EFER_LMA 0x000000400 /* Long mode active (R) */
103#define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */
104#define EFER_SVM 0x000001000 /* SVM enable bit for AMD, reserved
105 for Intel */
106#define EFER_LMSLE 0x000002000 /* Long Mode Segment Limit Enable */
107#define EFER_FFXSR 0x000004000 /* Fast FXSAVE/FSRSTOR */
108#define EFER_TCE 0x000008000 /* Translation Cache Extension */
109#define EFER_MCOMMIT 0x000020000 /* Enable MCOMMIT (AMD) */
110#define EFER_INTWB 0x000040000 /* Interruptible WBINVD */
111#define EFER_UAIE 0x000100000 /* Upper Address Ignore */
112#define EFER_AIBRSE 0x000200000 /* Automatic IBRS */
113
114/*
115 * Intel Extended Features registers
116 */
117#define XCR0 0 /* XFEATURE_ENABLED_MASK register */
118
119#define XFEATURE_ENABLED_X87 0x00000001
120#define XFEATURE_ENABLED_SSE 0x00000002
121#define XFEATURE_ENABLED_YMM_HI128 0x00000004
122#define XFEATURE_ENABLED_AVX XFEATURE_ENABLED_YMM_HI128
123#define XFEATURE_ENABLED_BNDREGS 0x00000008
124#define XFEATURE_ENABLED_BNDCSR 0x00000010
125#define XFEATURE_ENABLED_OPMASK 0x00000020
126#define XFEATURE_ENABLED_ZMM_HI256 0x00000040
127#define XFEATURE_ENABLED_HI16_ZMM 0x00000080
128#define XFEATURE_ENABLED_PKRU 0x00000200
129#define XFEATURE_ENABLED_TILECONFIG 0x00020000
130#define XFEATURE_ENABLED_TILEDATA 0x00040000
131
132#define XFEATURE_AVX \
133 (XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE | XFEATURE_ENABLED_AVX)
134#define XFEATURE_AVX512 \
135 (XFEATURE_ENABLED_OPMASK | XFEATURE_ENABLED_ZMM_HI256 | \
136 XFEATURE_ENABLED_HI16_ZMM)
137#define XFEATURE_MPX \
138 (XFEATURE_ENABLED_BNDREGS | XFEATURE_ENABLED_BNDCSR)
139
140/*
141 * CPUID instruction features register
142 */
143#define CPUID_FPU 0x00000001
144#define CPUID_VME 0x00000002
145#define CPUID_DE 0x00000004
146#define CPUID_PSE 0x00000008
147#define CPUID_TSC 0x00000010
148#define CPUID_MSR 0x00000020
149#define CPUID_PAE 0x00000040
150#define CPUID_MCE 0x00000080
151#define CPUID_CX8 0x00000100
152#define CPUID_APIC 0x00000200
153#define CPUID_B10 0x00000400
154#define CPUID_SEP 0x00000800
155#define CPUID_MTRR 0x00001000
156#define CPUID_PGE 0x00002000
157#define CPUID_MCA 0x00004000
158#define CPUID_CMOV 0x00008000
159#define CPUID_PAT 0x00010000
160#define CPUID_PSE36 0x00020000
161#define CPUID_PSN 0x00040000
162#define CPUID_CLFSH 0x00080000
163#define CPUID_B20 0x00100000
164#define CPUID_DS 0x00200000
165#define CPUID_ACPI 0x00400000
166#define CPUID_MMX 0x00800000
167#define CPUID_FXSR 0x01000000
168#define CPUID_SSE 0x02000000
169#define CPUID_XMM 0x02000000
170#define CPUID_SSE2 0x04000000
171#define CPUID_SS 0x08000000
172#define CPUID_HTT 0x10000000
173#define CPUID_TM 0x20000000
174#define CPUID_IA64 0x40000000
175#define CPUID_PBE 0x80000000
176
177#define CPUID2_SSE3 0x00000001
178#define CPUID2_PCLMULQDQ 0x00000002
179#define CPUID2_DTES64 0x00000004
180#define CPUID2_MON 0x00000008
181#define CPUID2_DS_CPL 0x00000010
182#define CPUID2_VMX 0x00000020
183#define CPUID2_SMX 0x00000040
184#define CPUID2_EST 0x00000080
185#define CPUID2_TM2 0x00000100
186#define CPUID2_SSSE3 0x00000200
187#define CPUID2_CNXTID 0x00000400
188#define CPUID2_SDBG 0x00000800
189#define CPUID2_FMA 0x00001000
190#define CPUID2_CX16 0x00002000
191#define CPUID2_XTPR 0x00004000
192#define CPUID2_PDCM 0x00008000
193#define CPUID2_PCID 0x00020000
194#define CPUID2_DCA 0x00040000
195#define CPUID2_SSE41 0x00080000
196#define CPUID2_SSE42 0x00100000
197#define CPUID2_X2APIC 0x00200000
198#define CPUID2_MOVBE 0x00400000
199#define CPUID2_POPCNT 0x00800000
200#define CPUID2_TSCDLT 0x01000000
201#define CPUID2_AESNI 0x02000000
202#define CPUID2_XSAVE 0x04000000
203#define CPUID2_OSXSAVE 0x08000000
204#define CPUID2_AVX 0x10000000
205#define CPUID2_F16C 0x20000000
206#define CPUID2_RDRAND 0x40000000
207#define CPUID2_HV 0x80000000
208
209/* Intel Processor Trace CPUID. */
210
211/* Leaf 0 ebx. */
212#define CPUPT_CR3 (1 << 0) /* CR3 Filtering Support */
213#define CPUPT_PSB (1 << 1) /* Configurable PSB and Cycle-Accurate Mode Supported */
214#define CPUPT_IPF (1 << 2) /* IP Filtering and TraceStop supported */
215#define CPUPT_MTC (1 << 3) /* MTC Supported */
216#define CPUPT_PRW (1 << 4) /* PTWRITE Supported */
217#define CPUPT_PWR (1 << 5) /* Power Event Trace Supported */
218
219/* Leaf 0 ecx. */
220#define CPUPT_TOPA (1 << 0) /* ToPA Output Supported */
221#define CPUPT_TOPA_MULTI (1 << 1) /* ToPA Tables Allow Multiple Output Entries */
222#define CPUPT_SINGLE (1 << 2) /* Single-Range Output Supported */
223#define CPUPT_TT_OUT (1 << 3) /* Output to Trace Transport Subsystem Supported */
224#define CPUPT_LINEAR_IP (1 << 31) /* IP Payloads are Linear IP, otherwise IP is effective */
225
226/* Leaf 1 eax. */
227#define CPUPT_NADDR_S 0 /* Number of Address Ranges */
228#define CPUPT_NADDR_M (0x7 << CPUPT_NADDR_S)
229#define CPUPT_MTC_BITMAP_S 16 /* Bitmap of supported MTC Period Encodings */
230#define CPUPT_MTC_BITMAP_M (0xffff << CPUPT_MTC_BITMAP_S)
231
232/* Leaf 1 ebx. */
233#define CPUPT_CT_BITMAP_S 0 /* Bitmap of supported Cycle Threshold values */
234#define CPUPT_CT_BITMAP_M (0xffff << CPUPT_CT_BITMAP_S)
235#define CPUPT_PFE_BITMAP_S 16 /* Bitmap of supported Configurable PSB Frequency encoding */
236#define CPUPT_PFE_BITMAP_M (0xffff << CPUPT_PFE_BITMAP_S)
237
238/*
239 * Important bits in the AMD extended cpuid flags
240 */
241#define AMDID_SYSCALL 0x00000800
242#define AMDID_MP 0x00080000
243#define AMDID_NX 0x00100000
244#define AMDID_EXT_MMX 0x00400000
245#define AMDID_FFXSR 0x02000000
246#define AMDID_PAGE1GB 0x04000000
247#define AMDID_RDTSCP 0x08000000
248#define AMDID_LM 0x20000000
249#define AMDID_EXT_3DNOW 0x40000000
250#define AMDID_3DNOW 0x80000000
251
252#define AMDID2_LAHF 0x00000001
253#define AMDID2_CMP 0x00000002
254#define AMDID2_SVM 0x00000004
255#define AMDID2_EXT_APIC 0x00000008
256#define AMDID2_CR8 0x00000010
257#define AMDID2_ABM 0x00000020
258#define AMDID2_SSE4A 0x00000040
259#define AMDID2_MAS 0x00000080
260#define AMDID2_PREFETCH 0x00000100
261#define AMDID2_OSVW 0x00000200
262#define AMDID2_IBS 0x00000400
263#define AMDID2_XOP 0x00000800
264#define AMDID2_SKINIT 0x00001000
265#define AMDID2_WDT 0x00002000
266#define AMDID2_LWP 0x00008000
267#define AMDID2_FMA4 0x00010000
268#define AMDID2_TCE 0x00020000
269#define AMDID2_NODE_ID 0x00080000
270#define AMDID2_TBM 0x00200000
271#define AMDID2_TOPOLOGY 0x00400000
272#define AMDID2_PCXC 0x00800000
273#define AMDID2_PNXC 0x01000000
274#define AMDID2_DBE 0x04000000
275#define AMDID2_PTSC 0x08000000
276#define AMDID2_PTSCEL2I 0x10000000
277#define AMDID2_MWAITX 0x20000000
278
279/*
280 * CPUID instruction 1 eax info
281 */
282#define CPUID_STEPPING 0x0000000f
283#define CPUID_MODEL 0x000000f0
284#define CPUID_FAMILY 0x00000f00
285#define CPUID_EXT_MODEL 0x000f0000
286#define CPUID_EXT_FAMILY 0x0ff00000
287#ifdef __i386__
288#define CPUID_TO_MODEL(id) \
289 ((((id) & CPUID_MODEL) >> 4) | \
290 ((((id) & CPUID_FAMILY) >= 0x600) ? \
291 (((id) & CPUID_EXT_MODEL) >> 12) : 0))
292#define CPUID_TO_FAMILY(id) \
293 ((((id) & CPUID_FAMILY) >> 8) + \
294 ((((id) & CPUID_FAMILY) == 0xf00) ? \
295 (((id) & CPUID_EXT_FAMILY) >> 20) : 0))
296#else
297#define CPUID_TO_MODEL(id) \
298 ((((id) & CPUID_MODEL) >> 4) | \
299 (((id) & CPUID_EXT_MODEL) >> 12))
300#define CPUID_TO_FAMILY(id) \
301 ((((id) & CPUID_FAMILY) >> 8) + \
302 (((id) & CPUID_EXT_FAMILY) >> 20))
303#endif
304#define CPUID_TO_STEPPING(id) ((id) & CPUID_STEPPING)
305
306/*
307 * CPUID instruction 1 ebx info
308 */
309#define CPUID_BRAND_INDEX 0x000000ff
310#define CPUID_CLFUSH_SIZE 0x0000ff00
311#define CPUID_HTT_CORES 0x00ff0000
312#define CPUID_LOCAL_APIC_ID 0xff000000
313
314/*
315 * CPUID instruction 5 info
316 */
317#define CPUID5_MON_MIN_SIZE 0x0000ffff /* eax */
318#define CPUID5_MON_MAX_SIZE 0x0000ffff /* ebx */
319#define CPUID5_MON_MWAIT_EXT 0x00000001 /* ecx */
320#define CPUID5_MWAIT_INTRBREAK 0x00000002 /* ecx */
321
322/*
323 * MWAIT cpu power states. Lower 4 bits are sub-states.
324 */
325#define MWAIT_C0 0xf0
326#define MWAIT_C1 0x00
327#define MWAIT_C2 0x10
328#define MWAIT_C3 0x20
329#define MWAIT_C4 0x30
330
331/*
332 * MWAIT extensions.
333 */
334/* Interrupt breaks MWAIT even when masked. */
335#define MWAIT_INTRBREAK 0x00000001
336
337/*
338 * CPUID leaf 6: Thermal and Power management.
339 */
340/* Eax. */
341#define CPUTPM1_SENSOR 0x00000001
342#define CPUTPM1_TURBO 0x00000002
343#define CPUTPM1_ARAT 0x00000004
344#define CPUTPM1_PLN 0x00000010
345#define CPUTPM1_ECMD 0x00000020
346#define CPUTPM1_PTM 0x00000040
347#define CPUTPM1_HWP 0x00000080
348#define CPUTPM1_HWP_NOTIFICATION 0x00000100
349#define CPUTPM1_HWP_ACTIVITY_WINDOW 0x00000200
350#define CPUTPM1_HWP_PERF_PREF 0x00000400
351#define CPUTPM1_HWP_PKG 0x00000800
352#define CPUTPM1_HDC 0x00002000
353#define CPUTPM1_TURBO30 0x00004000
354#define CPUTPM1_HWP_CAPABILITIES 0x00008000
355#define CPUTPM1_HWP_PECI_OVR 0x00010000
356#define CPUTPM1_HWP_FLEXIBLE 0x00020000
357#define CPUTPM1_HWP_FAST_MSR 0x00040000
358#define CPUTPM1_HW_FEEDBACK 0x00080000
359#define CPUTPM1_HWP_IGN_IDLE 0x00100000
360#define CPUTPM1_THREAD_DIRECTOR 0x00800000
361
362/* Ebx. */
363#define CPUTPM_B_NSENSINTTHRESH 0x0000000f
364
365/* Ecx. */
366#define CPUID_PERF_STAT 0x00000001
367#define CPUID_PERF_BIAS 0x00000008
368#define CPUID_PERF_TD_CLASSES 0x0000ff00
369
370/* Edx. */
371#define CPUID_HF_PERFORMANCE 0x00000001
372#define CPUID_HF_EFFICIENCY 0x00000002
373#define CPUID_TD_CAPABLITIES 0x0000000f
374#define CPUID_TD_TBLPAGES 0x00000f00
375
376/*
377 * CPUID instruction 0xb ebx info.
378 */
379#define CPUID_TYPE_INVAL 0
380#define CPUID_TYPE_SMT 1
381#define CPUID_TYPE_CORE 2
382
383/*
384 * CPUID instruction 0xd Processor Extended State Enumeration Sub-leaf 1
385 */
386#define CPUID_EXTSTATE_XSAVEOPT 0x00000001
387#define CPUID_EXTSTATE_XSAVEC 0x00000002
388#define CPUID_EXTSTATE_XINUSE 0x00000004
389#define CPUID_EXTSTATE_XSAVES 0x00000008
390
391/*
392 * AMD extended function 8000_0007h ebx info
393 */
394#define AMDRAS_MCA_OF_RECOV 0x00000001
395#define AMDRAS_SUCCOR 0x00000002
396#define AMDRAS_HW_ASSERT 0x00000004
397#define AMDRAS_SCALABLE_MCA 0x00000008
398#define AMDRAS_PFEH_SUPPORT 0x00000010
399
400/*
401 * AMD extended function 8000_0007h edx info
402 */
403#define AMDPM_TS 0x00000001
404#define AMDPM_FID 0x00000002
405#define AMDPM_VID 0x00000004
406#define AMDPM_TTP 0x00000008
407#define AMDPM_TM 0x00000010
408#define AMDPM_STC 0x00000020
409#define AMDPM_100MHZ_STEPS 0x00000040
410#define AMDPM_HW_PSTATE 0x00000080
411#define AMDPM_TSC_INVARIANT 0x00000100
412#define AMDPM_CPB 0x00000200
413
414/*
415 * AMD extended function 8000_0008h ebx info (amd_extended_feature_extensions)
416 */
417#define AMDFEID_CLZERO 0x00000001
418#define AMDFEID_IRPERF 0x00000002
419#define AMDFEID_XSAVEERPTR 0x00000004
420#define AMDFEID_INVLPGB 0x00000008
421#define AMDFEID_RDPRU 0x00000010
422#define AMDFEID_BE 0x00000040
423#define AMDFEID_MCOMMIT 0x00000100
424#define AMDFEID_WBNOINVD 0x00000200
425#define AMDFEID_IBPB 0x00001000
426#define AMDFEID_INT_WBINVD 0x00002000
427#define AMDFEID_IBRS 0x00004000
428#define AMDFEID_STIBP 0x00008000
429/* The below are only defined if the corresponding base feature above exists. */
430#define AMDFEID_IBRS_ALWAYSON 0x00010000
431#define AMDFEID_STIBP_ALWAYSON 0x00020000
432#define AMDFEID_PREFER_IBRS 0x00040000
433#define AMDFEID_SAMEMODE_IBRS 0x00080000
434#define AMDFEID_NO_LMSLE 0x00100000
435#define AMDFEID_INVLPGB_NEST 0x00200000
436#define AMDFEID_PPIN 0x00800000
437#define AMDFEID_SSBD 0x01000000
438/* SSBD via MSRC001_011F instead of MSR 0x48: */
439#define AMDFEID_VIRT_SSBD 0x02000000
440#define AMDFEID_SSB_NO 0x04000000
441#define AMDFEID_CPPC 0x08000000
442#define AMDFEID_PSFD 0x10000000
443#define AMDFEID_BTC_NO 0x20000000
444#define AMDFEID_IBPB_RET 0x40000000
445
446/*
447 * AMD extended function 8000_0008h ecx info
448 */
449#define AMDID_CMP_CORES 0x000000ff
450#define AMDID_COREID_SIZE 0x0000f000
451#define AMDID_COREID_SIZE_SHIFT 12
452
453/*
454 * AMD extended function 8000_0008h edx info
455 */
456#define AMDID_INVLPGB_MAXCNT 0x0000ffff
457#define AMDID_RDPRU_SHIFT 16
458#define AMDID_RDPRU_ID 0xffff0000
459
460/*
461 * CPUID instruction 7 Structured Extended Features, leaf 0 ebx info
462 */
463#define CPUID_STDEXT_FSGSBASE 0x00000001
464#define CPUID_STDEXT_TSC_ADJUST 0x00000002
465#define CPUID_STDEXT_SGX 0x00000004
466#define CPUID_STDEXT_BMI1 0x00000008
467#define CPUID_STDEXT_HLE 0x00000010
468#define CPUID_STDEXT_AVX2 0x00000020
469#define CPUID_STDEXT_FDP_EXC 0x00000040
470#define CPUID_STDEXT_SMEP 0x00000080
471#define CPUID_STDEXT_BMI2 0x00000100
472#define CPUID_STDEXT_ERMS 0x00000200
473#define CPUID_STDEXT_INVPCID 0x00000400
474#define CPUID_STDEXT_RTM 0x00000800
475#define CPUID_STDEXT_PQM 0x00001000
476#define CPUID_STDEXT_NFPUSG 0x00002000
477#define CPUID_STDEXT_MPX 0x00004000
478#define CPUID_STDEXT_PQE 0x00008000
479#define CPUID_STDEXT_AVX512F 0x00010000
480#define CPUID_STDEXT_AVX512DQ 0x00020000
481#define CPUID_STDEXT_RDSEED 0x00040000
482#define CPUID_STDEXT_ADX 0x00080000
483#define CPUID_STDEXT_SMAP 0x00100000
484#define CPUID_STDEXT_AVX512IFMA 0x00200000
485/* Formerly PCOMMIT */
486#define CPUID_STDEXT_CLFLUSHOPT 0x00800000
487#define CPUID_STDEXT_CLWB 0x01000000
488#define CPUID_STDEXT_PROCTRACE 0x02000000
489#define CPUID_STDEXT_AVX512PF 0x04000000
490#define CPUID_STDEXT_AVX512ER 0x08000000
491#define CPUID_STDEXT_AVX512CD 0x10000000
492#define CPUID_STDEXT_SHA 0x20000000
493#define CPUID_STDEXT_AVX512BW 0x40000000
494#define CPUID_STDEXT_AVX512VL 0x80000000
495
496/*
497 * CPUID instruction 7 Structured Extended Features, leaf 0 ecx info
498 */
499#define CPUID_STDEXT2_PREFETCHWT1 0x00000001
500#define CPUID_STDEXT2_AVX512VBMI 0x00000002
501#define CPUID_STDEXT2_UMIP 0x00000004
502#define CPUID_STDEXT2_PKU 0x00000008
503#define CPUID_STDEXT2_OSPKE 0x00000010
504#define CPUID_STDEXT2_WAITPKG 0x00000020
505#define CPUID_STDEXT2_AVX512VBMI2 0x00000040
506#define CPUID_STDEXT2_GFNI 0x00000100
507#define CPUID_STDEXT2_VAES 0x00000200
508#define CPUID_STDEXT2_VPCLMULQDQ 0x00000400
509#define CPUID_STDEXT2_AVX512VNNI 0x00000800
510#define CPUID_STDEXT2_AVX512BITALG 0x00001000
511#define CPUID_STDEXT2_TME 0x00002000
512#define CPUID_STDEXT2_AVX512VPOPCNTDQ 0x00004000
513#define CPUID_STDEXT2_LA57 0x00010000
514#define CPUID_STDEXT2_RDPID 0x00400000
515#define CPUID_STDEXT2_CLDEMOTE 0x02000000
516#define CPUID_STDEXT2_MOVDIRI 0x08000000
517#define CPUID_STDEXT2_MOVDIR64B 0x10000000
518#define CPUID_STDEXT2_ENQCMD 0x20000000
519#define CPUID_STDEXT2_SGXLC 0x40000000
520
521/*
522 * CPUID instruction 7 Structured Extended Features, leaf 0 edx info
523 */
524#define CPUID_STDEXT3_AVX5124VNNIW 0x00000004
525#define CPUID_STDEXT3_AVX5124FMAPS 0x00000008
526#define CPUID_STDEXT3_FSRM 0x00000010
527#define CPUID_STDEXT3_AVX512VP2INTERSECT 0x00000100
528#define CPUID_STDEXT3_MCUOPT 0x00000200
529#define CPUID_STDEXT3_MD_CLEAR 0x00000400
530#define CPUID_STDEXT3_TSXFA 0x00002000
531#define CPUID_STDEXT3_PCONFIG 0x00040000
532#define CPUID_STDEXT3_IBPB 0x04000000
533#define CPUID_STDEXT3_STIBP 0x08000000
534#define CPUID_STDEXT3_L1D_FLUSH 0x10000000
535#define CPUID_STDEXT3_ARCH_CAP 0x20000000
536#define CPUID_STDEXT3_CORE_CAP 0x40000000
537#define CPUID_STDEXT3_SSBD 0x80000000
538
539/*
540 * CPUID instruction 7 Structured Extended Features, leaf 1 eax info
541 */
542#define CPUID_STDEXT4_LASS 0x00000040
543#define CPUID_STDEXT4_LAM 0x04000000
544
545/* CPUID_HYBRID_ID leaf 0x1a */
546#define CPUID_HYBRID_CORE_MASK 0xff000000
547#define CPUID_HYBRID_SMALL_CORE 0x20000000
548#define CPUID_HYBRID_LARGE_CORE 0x40000000
549
550/* MSR IA32_ARCH_CAP(ABILITIES) bits */
551#define IA32_ARCH_CAP_RDCL_NO 0x00000001
552#define IA32_ARCH_CAP_IBRS_ALL 0x00000002
553#define IA32_ARCH_CAP_RSBA 0x00000004
554#define IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY 0x00000008
555#define IA32_ARCH_CAP_SSB_NO 0x00000010
556#define IA32_ARCH_CAP_MDS_NO 0x00000020
557#define IA32_ARCH_CAP_IF_PSCHANGE_MC_NO 0x00000040
558#define IA32_ARCH_CAP_TSX_CTRL 0x00000080
559#define IA32_ARCH_CAP_TAA_NO 0x00000100
560
561/* MSR IA32_TSX_CTRL bits */
562#define IA32_TSX_CTRL_RTM_DISABLE 0x00000001
563#define IA32_TSX_CTRL_TSX_CPUID_CLEAR 0x00000002
564
565/*
566 * CPUID manufacturers identifiers
567 */
568#define AMD_VENDOR_ID "AuthenticAMD"
569#define CENTAUR_VENDOR_ID "CentaurHauls"
570#define CYRIX_VENDOR_ID "CyrixInstead"
571#define INTEL_VENDOR_ID "GenuineIntel"
572#define NEXGEN_VENDOR_ID "NexGenDriven"
573#define NSC_VENDOR_ID "Geode by NSC"
574#define RISE_VENDOR_ID "RiseRiseRise"
575#define SIS_VENDOR_ID "SiS SiS SiS "
576#define TRANSMETA_VENDOR_ID "GenuineTMx86"
577#define UMC_VENDOR_ID "UMC UMC UMC "
578#define HYGON_VENDOR_ID "HygonGenuine"
579
580/*
581 * Model-specific registers for the i386 family
582 */
583#define MSR_P5_MC_ADDR 0x000
584#define MSR_P5_MC_TYPE 0x001
585#define MSR_TSC 0x010
586#define MSR_P5_CESR 0x011
587#define MSR_P5_CTR0 0x012
588#define MSR_P5_CTR1 0x013
589#define MSR_IA32_PLATFORM_ID 0x017
590#define MSR_APICBASE 0x01b
591#define MSR_EBL_CR_POWERON 0x02a
592#define MSR_TEST_CTL 0x033
593#define MSR_IA32_FEATURE_CONTROL 0x03a
594#define MSR_IA32_SPEC_CTRL 0x048
595#define MSR_IA32_PRED_CMD 0x049
596#define MSR_BIOS_UPDT_TRIG 0x079
597#define MSR_BBL_CR_D0 0x088
598#define MSR_BBL_CR_D1 0x089
599#define MSR_BBL_CR_D2 0x08a
600#define MSR_BIOS_SIGN 0x08b
601#define MSR_PERFCTR0 0x0c1
602#define MSR_PERFCTR1 0x0c2
603#define MSR_PLATFORM_INFO 0x0ce
604#define MSR_MPERF 0x0e7
605#define MSR_APERF 0x0e8
606#define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */
607#define MSR_MTRRcap 0x0fe
608#define MSR_IA32_ARCH_CAP 0x10a
609#define MSR_IA32_FLUSH_CMD 0x10b
610#define MSR_TSX_FORCE_ABORT 0x10f
611#define MSR_BBL_CR_ADDR 0x116
612#define MSR_BBL_CR_DECC 0x118
613#define MSR_BBL_CR_CTL 0x119
614#define MSR_BBL_CR_TRIG 0x11a
615#define MSR_BBL_CR_BUSY 0x11b
616#define MSR_BBL_CR_CTL3 0x11e
617#define MSR_IA32_TSX_CTRL 0x122
618#define MSR_IA32_MCU_OPT_CTRL 0x123
619#define MSR_MISC_FEATURE_ENABLES 0x140
620#define MSR_SYSENTER_CS_MSR 0x174
621#define MSR_SYSENTER_ESP_MSR 0x175
622#define MSR_SYSENTER_EIP_MSR 0x176
623#define MSR_MCG_CAP 0x179
624#define MSR_MCG_STATUS 0x17a
625#define MSR_MCG_CTL 0x17b
626#define MSR_EVNTSEL0 0x186
627#define MSR_EVNTSEL1 0x187
628#define MSR_THERM_CONTROL 0x19a
629#define MSR_THERM_INTERRUPT 0x19b
630#define MSR_THERM_STATUS 0x19c
631#define MSR_IA32_MISC_ENABLE 0x1a0
632#define MSR_IA32_TEMPERATURE_TARGET 0x1a2
633#define MSR_TURBO_RATIO_LIMIT 0x1ad
634#define MSR_TURBO_RATIO_LIMIT1 0x1ae
635#define MSR_IA32_ENERGY_PERF_BIAS 0x1b0
636#define MSR_IA32_PKG_THERM_STATUS 0x1b1
637#define MSR_IA32_PKG_THERM_INTERRUPT 0x1b2
638#define MSR_DEBUGCTLMSR 0x1d9
639#define MSR_LASTBRANCHFROMIP 0x1db
640#define MSR_LASTBRANCHTOIP 0x1dc
641#define MSR_LASTINTFROMIP 0x1dd
642#define MSR_LASTINTTOIP 0x1de
643#define MSR_ROB_CR_BKUPTMPDR6 0x1e0
644#define MSR_MTRRVarBase 0x200
645#define MSR_MTRR64kBase 0x250
646#define MSR_MTRR16kBase 0x258
647#define MSR_MTRR4kBase 0x268
648#define MSR_PAT 0x277
649#define MSR_MC0_CTL2 0x280
650#define MSR_MTRRdefType 0x2ff
651#define MSR_MC0_CTL 0x400
652#define MSR_MC0_STATUS 0x401
653#define MSR_MC0_ADDR 0x402
654#define MSR_MC0_MISC 0x403
655#define MSR_MC1_CTL 0x404
656#define MSR_MC1_STATUS 0x405
657#define MSR_MC1_ADDR 0x406
658#define MSR_MC1_MISC 0x407
659#define MSR_MC2_CTL 0x408
660#define MSR_MC2_STATUS 0x409
661#define MSR_MC2_ADDR 0x40a
662#define MSR_MC2_MISC 0x40b
663#define MSR_MC3_CTL 0x40c
664#define MSR_MC3_STATUS 0x40d
665#define MSR_MC3_ADDR 0x40e
666#define MSR_MC3_MISC 0x40f
667#define MSR_MC4_CTL 0x410
668#define MSR_MC4_STATUS 0x411
669#define MSR_MC4_ADDR 0x412
670#define MSR_MC4_MISC 0x413
671#define MSR_MCG_EXT_CTL 0x4d0
672#define MSR_RAPL_POWER_UNIT 0x606
673#define MSR_PKG_ENERGY_STATUS 0x611
674#define MSR_DRAM_ENERGY_STATUS 0x619
675#define MSR_PP0_ENERGY_STATUS 0x639
676#define MSR_PP1_ENERGY_STATUS 0x641
677#define MSR_PPERF 0x64e
678#define MSR_TSC_DEADLINE 0x6e0 /* Writes are not serializing */
679#define MSR_IA32_PM_ENABLE 0x770
680#define MSR_IA32_HWP_CAPABILITIES 0x771
681#define MSR_IA32_HWP_REQUEST_PKG 0x772
682#define MSR_IA32_HWP_INTERRUPT 0x773
683#define MSR_IA32_HWP_REQUEST 0x774
684#define MSR_IA32_HWP_STATUS 0x777
685
686/*
687 * VMX MSRs
688 */
689#define MSR_VMX_BASIC 0x480
690#define MSR_VMX_PINBASED_CTLS 0x481
691#define MSR_VMX_PROCBASED_CTLS 0x482
692#define MSR_VMX_EXIT_CTLS 0x483
693#define MSR_VMX_ENTRY_CTLS 0x484
694#define MSR_VMX_CR0_FIXED0 0x486
695#define MSR_VMX_CR0_FIXED1 0x487
696#define MSR_VMX_CR4_FIXED0 0x488
697#define MSR_VMX_CR4_FIXED1 0x489
698#define MSR_VMX_PROCBASED_CTLS2 0x48b
699#define MSR_VMX_EPT_VPID_CAP 0x48c
700#define MSR_VMX_TRUE_PINBASED_CTLS 0x48d
701#define MSR_VMX_TRUE_PROCBASED_CTLS 0x48e
702#define MSR_VMX_TRUE_EXIT_CTLS 0x48f
703#define MSR_VMX_TRUE_ENTRY_CTLS 0x490
704
705/*
706 * X2APIC MSRs.
707 * Writes are not serializing.
708 */
709#define MSR_APIC_000 0x800
710#define MSR_APIC_ID 0x802
711#define MSR_APIC_VERSION 0x803
712#define MSR_APIC_TPR 0x808
713#define MSR_APIC_EOI 0x80b
714#define MSR_APIC_LDR 0x80d
715#define MSR_APIC_SVR 0x80f
716#define MSR_APIC_ISR0 0x810
717#define MSR_APIC_ISR1 0x811
718#define MSR_APIC_ISR2 0x812
719#define MSR_APIC_ISR3 0x813
720#define MSR_APIC_ISR4 0x814
721#define MSR_APIC_ISR5 0x815
722#define MSR_APIC_ISR6 0x816
723#define MSR_APIC_ISR7 0x817
724#define MSR_APIC_TMR0 0x818
725#define MSR_APIC_IRR0 0x820
726#define MSR_APIC_ESR 0x828
727#define MSR_APIC_LVT_CMCI 0x82F
728#define MSR_APIC_ICR 0x830
729#define MSR_APIC_LVT_TIMER 0x832
730#define MSR_APIC_LVT_THERMAL 0x833
731#define MSR_APIC_LVT_PCINT 0x834
732#define MSR_APIC_LVT_LINT0 0x835
733#define MSR_APIC_LVT_LINT1 0x836
734#define MSR_APIC_LVT_ERROR 0x837
735#define MSR_APIC_ICR_TIMER 0x838
736#define MSR_APIC_CCR_TIMER 0x839
737#define MSR_APIC_DCR_TIMER 0x83e
738#define MSR_APIC_SELF_IPI 0x83f
739
740#define MSR_IA32_XSS 0xda0
741
742/*
743 * Intel Processor Trace (PT) MSRs.
744 */
745#define MSR_IA32_RTIT_OUTPUT_BASE 0x560 /* Trace Output Base Register (R/W) */
746#define MSR_IA32_RTIT_OUTPUT_MASK_PTRS 0x561 /* Trace Output Mask Pointers Register (R/W) */
747#define MSR_IA32_RTIT_CTL 0x570 /* Trace Control Register (R/W) */
748#define RTIT_CTL_TRACEEN (1 << 0)
749#define RTIT_CTL_CYCEN (1 << 1)
750#define RTIT_CTL_OS (1 << 2)
751#define RTIT_CTL_USER (1 << 3)
752#define RTIT_CTL_PWREVTEN (1 << 4)
753#define RTIT_CTL_FUPONPTW (1 << 5)
754#define RTIT_CTL_FABRICEN (1 << 6)
755#define RTIT_CTL_CR3FILTER (1 << 7)
756#define RTIT_CTL_TOPA (1 << 8)
757#define RTIT_CTL_MTCEN (1 << 9)
758#define RTIT_CTL_TSCEN (1 << 10)
759#define RTIT_CTL_DISRETC (1 << 11)
760#define RTIT_CTL_PTWEN (1 << 12)
761#define RTIT_CTL_BRANCHEN (1 << 13)
762#define RTIT_CTL_MTC_FREQ_S 14
763#define RTIT_CTL_MTC_FREQ(n) ((n) << RTIT_CTL_MTC_FREQ_S)
764#define RTIT_CTL_MTC_FREQ_M (0xf << RTIT_CTL_MTC_FREQ_S)
765#define RTIT_CTL_CYC_THRESH_S 19
766#define RTIT_CTL_CYC_THRESH_M (0xf << RTIT_CTL_CYC_THRESH_S)
767#define RTIT_CTL_PSB_FREQ_S 24
768#define RTIT_CTL_PSB_FREQ_M (0xf << RTIT_CTL_PSB_FREQ_S)
769#define RTIT_CTL_ADDR_CFG_S(n) (32 + (n) * 4)
770#define RTIT_CTL_ADDR0_CFG_S 32
771#define RTIT_CTL_ADDR0_CFG_M (0xfULL << RTIT_CTL_ADDR0_CFG_S)
772#define RTIT_CTL_ADDR1_CFG_S 36
773#define RTIT_CTL_ADDR1_CFG_M (0xfULL << RTIT_CTL_ADDR1_CFG_S)
774#define RTIT_CTL_ADDR2_CFG_S 40
775#define RTIT_CTL_ADDR2_CFG_M (0xfULL << RTIT_CTL_ADDR2_CFG_S)
776#define RTIT_CTL_ADDR3_CFG_S 44
777#define RTIT_CTL_ADDR3_CFG_M (0xfULL << RTIT_CTL_ADDR3_CFG_S)
778#define MSR_IA32_RTIT_STATUS 0x571 /* Tracing Status Register (R/W) */
779#define RTIT_STATUS_FILTEREN (1 << 0)
780#define RTIT_STATUS_CONTEXTEN (1 << 1)
781#define RTIT_STATUS_TRIGGEREN (1 << 2)
782#define RTIT_STATUS_ERROR (1 << 4)
783#define RTIT_STATUS_STOPPED (1 << 5)
784#define RTIT_STATUS_PACKETBYTECNT_S 32
785#define RTIT_STATUS_PACKETBYTECNT_M (0x1ffffULL << RTIT_STATUS_PACKETBYTECNT_S)
786#define MSR_IA32_RTIT_CR3_MATCH 0x572 /* Trace Filter CR3 Match Register (R/W) */
787#define MSR_IA32_RTIT_ADDR_A(n) (0x580 + (n) * 2)
788#define MSR_IA32_RTIT_ADDR_B(n) (0x581 + (n) * 2)
789#define MSR_IA32_RTIT_ADDR0_A 0x580 /* Region 0 Start Address (R/W) */
790#define MSR_IA32_RTIT_ADDR0_B 0x581 /* Region 0 End Address (R/W) */
791#define MSR_IA32_RTIT_ADDR1_A 0x582 /* Region 1 Start Address (R/W) */
792#define MSR_IA32_RTIT_ADDR1_B 0x583 /* Region 1 End Address (R/W) */
793#define MSR_IA32_RTIT_ADDR2_A 0x584 /* Region 2 Start Address (R/W) */
794#define MSR_IA32_RTIT_ADDR2_B 0x585 /* Region 2 End Address (R/W) */
795#define MSR_IA32_RTIT_ADDR3_A 0x586 /* Region 3 Start Address (R/W) */
796#define MSR_IA32_RTIT_ADDR3_B 0x587 /* Region 3 End Address (R/W) */
797
798/* Intel Processor Trace Table of Physical Addresses (ToPA). */
799#define TOPA_SIZE_S 6
800#define TOPA_SIZE_M (0xf << TOPA_SIZE_S)
801#define TOPA_SIZE_4K (0 << TOPA_SIZE_S)
802#define TOPA_SIZE_8K (1 << TOPA_SIZE_S)
803#define TOPA_SIZE_16K (2 << TOPA_SIZE_S)
804#define TOPA_SIZE_32K (3 << TOPA_SIZE_S)
805#define TOPA_SIZE_64K (4 << TOPA_SIZE_S)
806#define TOPA_SIZE_128K (5 << TOPA_SIZE_S)
807#define TOPA_SIZE_256K (6 << TOPA_SIZE_S)
808#define TOPA_SIZE_512K (7 << TOPA_SIZE_S)
809#define TOPA_SIZE_1M (8 << TOPA_SIZE_S)
810#define TOPA_SIZE_2M (9 << TOPA_SIZE_S)
811#define TOPA_SIZE_4M (10 << TOPA_SIZE_S)
812#define TOPA_SIZE_8M (11 << TOPA_SIZE_S)
813#define TOPA_SIZE_16M (12 << TOPA_SIZE_S)
814#define TOPA_SIZE_32M (13 << TOPA_SIZE_S)
815#define TOPA_SIZE_64M (14 << TOPA_SIZE_S)
816#define TOPA_SIZE_128M (15 << TOPA_SIZE_S)
817#define TOPA_STOP (1 << 4)
818#define TOPA_INT (1 << 2)
819#define TOPA_END (1 << 0)
820
821/*
822 * Intel Hardware Feedback Interface / Thread Director MSRs
823 */
824#define MSR_IA32_HW_FEEDBACK_PTR 0x17d0
825#define MSR_IA32_HW_FEEDBACK_CONFIG 0x17d1
826#define MSR_IA32_THREAD_FEEDBACK_CHAR 0x17d2
827#define MSR_IA32_HW_FEEDBACK_THREAD_CONFIG 0x17d4
828
829/*
830 * Constants related to MSR's.
831 */
832#define APICBASE_RESERVED 0x000002ff
833#define APICBASE_BSP 0x00000100
834#define APICBASE_X2APIC 0x00000400
835#define APICBASE_ENABLED 0x00000800
836#define APICBASE_ADDRESS 0xfffff000
837
838/* MSR_IA32_FEATURE_CONTROL related */
839#define IA32_FEATURE_CONTROL_LOCK 0x01 /* lock bit */
840#define IA32_FEATURE_CONTROL_SMX_EN 0x02 /* enable VMX inside SMX */
841#define IA32_FEATURE_CONTROL_VMX_EN 0x04 /* enable VMX outside SMX */
842#define IA32_FEATURE_CONTROL_LMCE_EN 0x100000 /* enable local MCE */
843
844/* MSR IA32_MISC_ENABLE */
845#define IA32_MISC_EN_FASTSTR 0x0000000000000001ULL
846#define IA32_MISC_EN_ATCCE 0x0000000000000008ULL
847#define IA32_MISC_EN_PERFMON 0x0000000000000080ULL
848#define IA32_MISC_EN_PEBSU 0x0000000000001000ULL
849#define IA32_MISC_EN_ESSTE 0x0000000000010000ULL
850#define IA32_MISC_EN_MONE 0x0000000000040000ULL
851#define IA32_MISC_EN_LIMCPUID 0x0000000000400000ULL
852#define IA32_MISC_EN_xTPRD 0x0000000000800000ULL
853#define IA32_MISC_EN_XDD 0x0000000400000000ULL
854
855/*
856 * IA32_SPEC_CTRL and IA32_PRED_CMD MSRs are described in the Intel'
857 * document 336996-001 Speculative Execution Side Channel Mitigations.
858 *
859 * AMD uses the same MSRs and bit definitions, as described in 111006-B
860 * "Indirect Branch Control Extension" and 124441 "Speculative Store Bypass
861 * Disable."
862 */
863/* MSR IA32_SPEC_CTRL */
864#define IA32_SPEC_CTRL_IBRS 0x00000001
865#define IA32_SPEC_CTRL_STIBP 0x00000002
866#define IA32_SPEC_CTRL_SSBD 0x00000004
867
868/* MSR IA32_PRED_CMD */
869#define IA32_PRED_CMD_IBPB_BARRIER 0x0000000000000001ULL
870
871/* MSR IA32_FLUSH_CMD */
872#define IA32_FLUSH_CMD_L1D 0x00000001
873
874/* MSR IA32_MCU_OPT_CTRL */
875#define IA32_RNGDS_MITG_DIS 0x00000001
876
877/* MSR IA32_HWP_CAPABILITIES */
878#define IA32_HWP_CAPABILITIES_HIGHEST_PERFORMANCE(x) (((x) >> 0) & 0xff)
879#define IA32_HWP_CAPABILITIES_GUARANTEED_PERFORMANCE(x) (((x) >> 8) & 0xff)
880#define IA32_HWP_CAPABILITIES_EFFICIENT_PERFORMANCE(x) (((x) >> 16) & 0xff)
881#define IA32_HWP_CAPABILITIES_LOWEST_PERFORMANCE(x) (((x) >> 24) & 0xff)
882
883/* MSR IA32_HWP_REQUEST */
884#define IA32_HWP_REQUEST_MINIMUM_VALID (1ULL << 63)
885#define IA32_HWP_REQUEST_MAXIMUM_VALID (1ULL << 62)
886#define IA32_HWP_REQUEST_DESIRED_VALID (1ULL << 61)
887#define IA32_HWP_REQUEST_EPP_VALID (1ULL << 60)
888#define IA32_HWP_REQUEST_ACTIVITY_WINDOW_VALID (1ULL << 59)
889#define IA32_HWP_REQUEST_PACKAGE_CONTROL (1ULL << 42)
890#define IA32_HWP_ACTIVITY_WINDOW (0x3ffULL << 32)
891#define IA32_HWP_REQUEST_ENERGY_PERFORMANCE_PREFERENCE (0xffULL << 24)
892#define IA32_HWP_DESIRED_PERFORMANCE (0xffULL << 16)
893#define IA32_HWP_REQUEST_MAXIMUM_PERFORMANCE (0xffULL << 8)
894#define IA32_HWP_MINIMUM_PERFORMANCE (0xffULL << 0)
895
896/* MSR IA32_ENERGY_PERF_BIAS */
897#define IA32_ENERGY_PERF_BIAS_POLICY_HINT_MASK (0xfULL << 0)
898
899/* MSR IA32_HW_FEEDBACK_PTR */
900#define IA32_HW_FEEDBACK_PTR_ENABLE (0x1ULL << 0)
901
902/* MSR IA32_HW_FEEDBACK_CONFIG */
903#define IA32_HW_FEEDBACK_CONFIG_EN_HFI (0x1ULL << 0)
904#define IA32_HW_FEEDBACK_CONFIG_EN_THDIR (0x1ULL << 1)
905
906/* MSR IA32_PKG_THERM_STATUS */
907#define IA32_PKG_THERM_STATUS_HFI_UPDATED (0x1ULL << 26)
908
909/* MSR IA32_PKG_THERM_INTERRUPT */
910#define IA32_PKG_THERM_INTERRUPT_HFI_ENABLE (0x1ULL << 25)
911
912/*
913 * PAT modes.
914 */
915#define PAT_UNCACHEABLE 0x00
916#define PAT_WRITE_COMBINING 0x01
917#define PAT_WRITE_THROUGH 0x04
918#define PAT_WRITE_PROTECTED 0x05
919#define PAT_WRITE_BACK 0x06
920#define PAT_UNCACHED 0x07
921#define PAT_VALUE(i, m) ((long long)(m) << (8 * (i)))
922#define PAT_MASK(i) PAT_VALUE(i, 0xff)
923
924/*
925 * Constants related to MTRRs
926 */
927#define MTRR_UNCACHEABLE 0x00
928#define MTRR_WRITE_COMBINING 0x01
929#define MTRR_WRITE_THROUGH 0x04
930#define MTRR_WRITE_PROTECTED 0x05
931#define MTRR_WRITE_BACK 0x06
932#define MTRR_N64K 8 /* numbers of fixed-size entries */
933#define MTRR_N16K 16
934#define MTRR_N4K 64
935#define MTRR_CAP_WC 0x0000000000000400
936#define MTRR_CAP_FIXED 0x0000000000000100
937#define MTRR_CAP_VCNT 0x00000000000000ff
938#define MTRR_DEF_ENABLE 0x0000000000000800
939#define MTRR_DEF_FIXED_ENABLE 0x0000000000000400
940#define MTRR_DEF_TYPE 0x00000000000000ff
941#define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000
942#define MTRR_PHYSBASE_TYPE 0x00000000000000ff
943#define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000
944#define MTRR_PHYSMASK_VALID 0x0000000000000800
945
946/*
947 * Cyrix configuration registers, accessible as IO ports.
948 */
949#define CCR0 0xc0 /* Configuration control register 0 */
950#define CCR0_NC0 0x01 /* First 64K of each 1M memory region is
951 non-cacheable */
952#define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */
953#define CCR0_A20M 0x04 /* Enables A20M# input pin */
954#define CCR0_KEN 0x08 /* Enables KEN# input pin */
955#define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */
956#define CCR0_BARB 0x20 /* Flushes internal cache when entering hold
957 state */
958#define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set
959 assoc */
960#define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */
961
962#define CCR1 0xc1 /* Configuration control register 1 */
963#define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */
964#define CCR1_SMI 0x02 /* Enables SMM pins */
965#define CCR1_SMAC 0x04 /* System management memory access */
966#define CCR1_MMAC 0x08 /* Main memory access */
967#define CCR1_NO_LOCK 0x10 /* Negate LOCK# */
968#define CCR1_SM3 0x80 /* SMM address space address region 3 */
969
970#define CCR2 0xc2
971#define CCR2_WB 0x02 /* Enables WB cache interface pins */
972#define CCR2_SADS 0x02 /* Slow ADS */
973#define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */
974#define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */
975#define CCR2_WT1 0x10 /* WT region 1 */
976#define CCR2_WPR1 0x10 /* Write-protect region 1 */
977#define CCR2_BARB 0x20 /* Flushes write-back cache when entering
978 hold state. */
979#define CCR2_BWRT 0x40 /* Enables burst write cycles */
980#define CCR2_USE_SUSP 0x80 /* Enables suspend pins */
981
982#define CCR3 0xc3
983#define CCR3_SMILOCK 0x01 /* SMM register lock */
984#define CCR3_NMI 0x02 /* Enables NMI during SMM */
985#define CCR3_LINBRST 0x04 /* Linear address burst cycles */
986#define CCR3_SMMMODE 0x08 /* SMM Mode */
987#define CCR3_MAPEN0 0x10 /* Enables Map0 */
988#define CCR3_MAPEN1 0x20 /* Enables Map1 */
989#define CCR3_MAPEN2 0x40 /* Enables Map2 */
990#define CCR3_MAPEN3 0x80 /* Enables Map3 */
991
992#define CCR4 0xe8
993#define CCR4_IOMASK 0x07
994#define CCR4_MEM 0x08 /* Enables momory bypassing */
995#define CCR4_DTE 0x10 /* Enables directory table entry cache */
996#define CCR4_FASTFPE 0x20 /* Fast FPU exception */
997#define CCR4_CPUID 0x80 /* Enables CPUID instruction */
998
999#define CCR5 0xe9
1000#define CCR5_WT_ALLOC 0x01 /* Write-through allocate */
1001#define CCR5_SLOP 0x02 /* LOOP instruction slowed down */
1002#define CCR5_LBR1 0x10 /* Local bus region 1 */
1003#define CCR5_ARREN 0x20 /* Enables ARR region */
1004
1005#define CCR6 0xea
1006
1007#define CCR7 0xeb
1008
1009/* Performance Control Register (5x86 only). */
1010#define PCR0 0x20
1011#define PCR0_RSTK 0x01 /* Enables return stack */
1012#define PCR0_BTB 0x02 /* Enables branch target buffer */
1013#define PCR0_LOOP 0x04 /* Enables loop */
1014#define PCR0_AIS 0x08 /* Enables all instrcutions stalled to
1015 serialize pipe. */
1016#define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */
1017#define PCR0_BTBRT 0x40 /* Enables BTB test register. */
1018#define PCR0_LSSER 0x80 /* Disable reorder */
1019
1020/* Device Identification Registers */
1021#define DIR0 0xfe
1022#define DIR1 0xff
1023
1024/*
1025 * Machine Check register constants.
1026 */
1027#define MCG_CAP_COUNT 0x000000ff
1028#define MCG_CAP_CTL_P 0x00000100
1029#define MCG_CAP_EXT_P 0x00000200
1030#define MCG_CAP_CMCI_P 0x00000400
1031#define MCG_CAP_TES_P 0x00000800
1032#define MCG_CAP_EXT_CNT 0x00ff0000
1033#define MCG_CAP_SER_P 0x01000000
1034#define MCG_CAP_EMC_P 0x02000000
1035#define MCG_CAP_ELOG_P 0x04000000
1036#define MCG_CAP_LMCE_P 0x08000000
1037#define MCG_STATUS_RIPV 0x00000001
1038#define MCG_STATUS_EIPV 0x00000002
1039#define MCG_STATUS_MCIP 0x00000004
1040#define MCG_STATUS_LMCS 0x00000008 /* if MCG_CAP_LMCE_P */
1041#define MCG_CTL_ENABLE 0xffffffffffffffff
1042#define MCG_CTL_DISABLE 0x0000000000000000
1043#define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4)
1044#define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4)
1045#define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4)
1046#define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4)
1047#define MSR_MC_CTL2(x) (MSR_MC0_CTL2 + (x)) /* If MCG_CAP_CMCI_P */
1048#define MC_STATUS_MCA_ERROR 0x000000000000ffff
1049#define MC_STATUS_MODEL_ERROR 0x00000000ffff0000
1050#define MC_STATUS_OTHER_INFO 0x01ffffff00000000
1051#define MC_STATUS_COR_COUNT 0x001fffc000000000 /* If MCG_CAP_CMCI_P */
1052#define MC_STATUS_TES_STATUS 0x0060000000000000 /* If MCG_CAP_TES_P */
1053#define MC_STATUS_AR 0x0080000000000000 /* If MCG_CAP_TES_P */
1054#define MC_STATUS_S 0x0100000000000000 /* If MCG_CAP_TES_P */
1055#define MC_STATUS_PCC 0x0200000000000000
1056#define MC_STATUS_ADDRV 0x0400000000000000
1057#define MC_STATUS_MISCV 0x0800000000000000
1058#define MC_STATUS_EN 0x1000000000000000
1059#define MC_STATUS_UC 0x2000000000000000
1060#define MC_STATUS_OVER 0x4000000000000000
1061#define MC_STATUS_VAL 0x8000000000000000
1062#define MC_MISC_RA_LSB 0x000000000000003f /* If MCG_CAP_SER_P */
1063#define MC_MISC_ADDRESS_MODE 0x00000000000001c0 /* If MCG_CAP_SER_P */
1064#define MC_MISC_PCIE_RID 0x00000000ffff0000
1065#define MC_MISC_PCIE_FUNC 0x0000000000070000
1066#define MC_MISC_PCIE_SLOT 0x0000000000f80000
1067#define MC_MISC_PCIE_BUS 0x00000000ff000000
1068#define MC_MISC_PCIE_SEG 0x000000ff00000000
1069#define MC_CTL2_THRESHOLD 0x0000000000007fff
1070#define MC_CTL2_CMCI_EN 0x0000000040000000
1071#define MC_AMDNB_BANK 4
1072#define MC_MISC_AMD_VAL 0x8000000000000000 /* Counter presence valid */
1073#define MC_MISC_AMD_CNTP 0x4000000000000000 /* Counter present */
1074#define MC_MISC_AMD_LOCK 0x2000000000000000 /* Register locked */
1075#define MC_MISC_AMD_INTP 0x1000000000000000 /* Int. type can generate interrupts */
1076#define MC_MISC_AMD_LVT_MASK 0x00f0000000000000 /* Extended LVT offset */
1077#define MC_MISC_AMD_LVT_SHIFT 52
1078#define MC_MISC_AMD_CNTEN 0x0008000000000000 /* Counter enabled */
1079#define MC_MISC_AMD_INT_MASK 0x0006000000000000 /* Interrupt type */
1080#define MC_MISC_AMD_INT_LVT 0x0002000000000000 /* Interrupt via Extended LVT */
1081#define MC_MISC_AMD_INT_SMI 0x0004000000000000 /* SMI */
1082#define MC_MISC_AMD_OVERFLOW 0x0001000000000000 /* Counter overflow */
1083#define MC_MISC_AMD_CNT_MASK 0x00000fff00000000 /* Counter value */
1084#define MC_MISC_AMD_CNT_SHIFT 32
1085#define MC_MISC_AMD_CNT_MAX 0xfff
1086#define MC_MISC_AMD_PTR_MASK 0x00000000ff000000 /* Pointer to additional registers */
1087#define MC_MISC_AMD_PTR_SHIFT 24
1088
1089/* AMD Scalable MCA */
1090#define MSR_SMCA_MC0_CTL 0xc0002000
1091#define MSR_SMCA_MC0_STATUS 0xc0002001
1092#define MSR_SMCA_MC0_ADDR 0xc0002002
1093#define MSR_SMCA_MC0_MISC0 0xc0002003
1094#define MSR_SMCA_MC_CTL(x) (MSR_SMCA_MC0_CTL + 0x10 * (x))
1095#define MSR_SMCA_MC_STATUS(x) (MSR_SMCA_MC0_STATUS + 0x10 * (x))
1096#define MSR_SMCA_MC_ADDR(x) (MSR_SMCA_MC0_ADDR + 0x10 * (x))
1097#define MSR_SMCA_MC_MISC(x) (MSR_SMCA_MC0_MISC0 + 0x10 * (x))
1098
1099/*
1100 * The following four 3-byte registers control the non-cacheable regions.
1101 * These registers must be written as three separate bytes.
1102 *
1103 * NCRx+0: A31-A24 of starting address
1104 * NCRx+1: A23-A16 of starting address
1105 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
1106 *
1107 * The non-cacheable region's starting address must be aligned to the
1108 * size indicated by the NCR_SIZE_xx field.
1109 */
1110#define NCR1 0xc4
1111#define NCR2 0xc7
1112#define NCR3 0xca
1113#define NCR4 0xcd
1114
1115#define NCR_SIZE_0K 0
1116#define NCR_SIZE_4K 1
1117#define NCR_SIZE_8K 2
1118#define NCR_SIZE_16K 3
1119#define NCR_SIZE_32K 4
1120#define NCR_SIZE_64K 5
1121#define NCR_SIZE_128K 6
1122#define NCR_SIZE_256K 7
1123#define NCR_SIZE_512K 8
1124#define NCR_SIZE_1M 9
1125#define NCR_SIZE_2M 10
1126#define NCR_SIZE_4M 11
1127#define NCR_SIZE_8M 12
1128#define NCR_SIZE_16M 13
1129#define NCR_SIZE_32M 14
1130#define NCR_SIZE_4G 15
1131
1132/*
1133 * The address region registers are used to specify the location and
1134 * size for the eight address regions.
1135 *
1136 * ARRx + 0: A31-A24 of start address
1137 * ARRx + 1: A23-A16 of start address
1138 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx
1139 */
1140#define ARR0 0xc4
1141#define ARR1 0xc7
1142#define ARR2 0xca
1143#define ARR3 0xcd
1144#define ARR4 0xd0
1145#define ARR5 0xd3
1146#define ARR6 0xd6
1147#define ARR7 0xd9
1148
1149#define ARR_SIZE_0K 0
1150#define ARR_SIZE_4K 1
1151#define ARR_SIZE_8K 2
1152#define ARR_SIZE_16K 3
1153#define ARR_SIZE_32K 4
1154#define ARR_SIZE_64K 5
1155#define ARR_SIZE_128K 6
1156#define ARR_SIZE_256K 7
1157#define ARR_SIZE_512K 8
1158#define ARR_SIZE_1M 9
1159#define ARR_SIZE_2M 10
1160#define ARR_SIZE_4M 11
1161#define ARR_SIZE_8M 12
1162#define ARR_SIZE_16M 13
1163#define ARR_SIZE_32M 14
1164#define ARR_SIZE_4G 15
1165
1166/*
1167 * The region control registers specify the attributes associated with
1168 * the ARRx addres regions.
1169 */
1170#define RCR0 0xdc
1171#define RCR1 0xdd
1172#define RCR2 0xde
1173#define RCR3 0xdf
1174#define RCR4 0xe0
1175#define RCR5 0xe1
1176#define RCR6 0xe2
1177#define RCR7 0xe3
1178
1179#define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */
1180#define RCR_RCE 0x01 /* Enables caching for ARR7. */
1181#define RCR_WWO 0x02 /* Weak write ordering. */
1182#define RCR_WL 0x04 /* Weak locking. */
1183#define RCR_WG 0x08 /* Write gathering. */
1184#define RCR_WT 0x10 /* Write-through. */
1185#define RCR_NLB 0x20 /* LBA# pin is not asserted. */
1186
1187/* AMD Write Allocate Top-Of-Memory and Control Register */
1188#define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */
1189#define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */
1190#define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */
1191
1192/* AMD64 MSR's */
1193#define MSR_EFER 0xc0000080 /* extended features */
1194#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */
1195#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */
1196#define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target rip */
1197#define MSR_SF_MASK 0xc0000084 /* syscall flags mask */
1198#define MSR_FSBASE 0xc0000100 /* base address of the %fs "segment" */
1199#define MSR_GSBASE 0xc0000101 /* base address of the %gs "segment" */
1200#define MSR_KGSBASE 0xc0000102 /* base address of the kernel %gs */
1201#define MSR_TSC_AUX 0xc0000103
1202#define MSR_PERFEVSEL0 0xc0010000
1203#define MSR_PERFEVSEL1 0xc0010001
1204#define MSR_PERFEVSEL2 0xc0010002
1205#define MSR_PERFEVSEL3 0xc0010003
1206#define MSR_K7_PERFCTR0 0xc0010004
1207#define MSR_K7_PERFCTR1 0xc0010005
1208#define MSR_K7_PERFCTR2 0xc0010006
1209#define MSR_K7_PERFCTR3 0xc0010007
1210#define MSR_SYSCFG 0xc0010010
1211#define MSR_HWCR 0xc0010015
1212#define MSR_IORRBASE0 0xc0010016
1213#define MSR_IORRMASK0 0xc0010017
1214#define MSR_IORRBASE1 0xc0010018
1215#define MSR_IORRMASK1 0xc0010019
1216#define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */
1217#define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */
1218#define MSR_NB_CFG1 0xc001001f /* NB configuration 1 */
1219#define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */
1220#define MSR_MC0_CTL_MASK 0xc0010044
1221#define MSR_AMDK8_IPM 0xc0010055
1222#define MSR_P_STATE_LIMIT 0xc0010061 /* P-state Current Limit Register */
1223#define MSR_P_STATE_CONTROL 0xc0010062 /* P-state Control Register */
1224#define MSR_P_STATE_STATUS 0xc0010063 /* P-state Status Register */
1225#define MSR_P_STATE_CONFIG(n) (0xc0010064 + (n)) /* P-state Config */
1226#define MSR_SMM_ADDR 0xc0010112 /* SMM TSEG base address */
1227#define MSR_SMM_MASK 0xc0010113 /* SMM TSEG address mask */
1228#define MSR_VM_CR 0xc0010114 /* SVM: feature control */
1229#define MSR_VM_HSAVE_PA 0xc0010117 /* SVM: host save area address */
1230#define MSR_AMD_CPUID07 0xc0011002 /* CPUID 07 %ebx override */
1231#define MSR_EXTFEATURES 0xc0011005 /* Extended CPUID Features override */
1232#define MSR_LS_CFG 0xc0011020
1233#define MSR_IC_CFG 0xc0011021 /* Instruction Cache Configuration */
1234#define MSR_DE_CFG 0xc0011029 /* Decode Configuration */
1235
1236/* MSR_AMDK8_IPM */
1237#define AMDK8_SMIONCMPHALT (1ULL << 27)
1238#define AMDK8_C1EONCMPHALT (1ULL << 28)
1239
1240/* MSR_VM_CR related */
1241#define VM_CR_SVMDIS 0x10 /* SVM: disabled by BIOS */
1242
1243/* MSR_DE_CFG */
1244#define DE_CFG_10H_12H_STACK_POINTER_JUMP_FIX_BIT 0x1
1245#define DE_CFG_ZEN_LOAD_STALE_DATA_FIX_BIT 0x2000
1246#define DE_CFG_ZEN2_FP_BACKUP_FIX_BIT 0x200
1247
1248/* VIA ACE crypto featureset: for via_feature_rng */
1249#define VIA_HAS_RNG 1 /* cpu has RNG */
1250
1251/* VIA ACE crypto featureset: for via_feature_xcrypt */
1252#define VIA_HAS_AES 1 /* cpu has AES */
1253#define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */
1254#define VIA_HAS_MM 4 /* cpu has RSA instructions */
1255#define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */
1256
1257/* Centaur Extended Feature flags */
1258#define VIA_CPUID_HAS_RNG 0x000004
1259#define VIA_CPUID_DO_RNG 0x000008
1260#define VIA_CPUID_HAS_ACE 0x000040
1261#define VIA_CPUID_DO_ACE 0x000080
1262#define VIA_CPUID_HAS_ACE2 0x000100
1263#define VIA_CPUID_DO_ACE2 0x000200
1264#define VIA_CPUID_HAS_PHE 0x000400
1265#define VIA_CPUID_DO_PHE 0x000800
1266#define VIA_CPUID_HAS_PMM 0x001000
1267#define VIA_CPUID_DO_PMM 0x002000
1268
1269/* VIA ACE xcrypt-* instruction context control options */
1270#define VIA_CRYPT_CWLO_ROUND_M 0x0000000f
1271#define VIA_CRYPT_CWLO_ALG_M 0x00000070
1272#define VIA_CRYPT_CWLO_ALG_AES 0x00000000
1273#define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080
1274#define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000
1275#define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080
1276#define VIA_CRYPT_CWLO_NORMAL 0x00000000
1277#define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100
1278#define VIA_CRYPT_CWLO_ENCRYPT 0x00000000
1279#define VIA_CRYPT_CWLO_DECRYPT 0x00000200
1280#define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */
1281#define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */
1282#define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */
1283
1284#endif /* !_MACHINE_SPECIALREG_H_ */