master
1/*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2003-2008, Joseph Koshy
5 * Copyright (c) 2007 The FreeBSD Foundation
6 * All rights reserved.
7 *
8 * Portions of this software were developed by A. Joseph Koshy under
9 * sponsorship from the FreeBSD Foundation and Google, Inc.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 */
32
33#ifndef _SYS_PMC_H_
34#define _SYS_PMC_H_
35
36#include <dev/hwpmc/pmc_events.h>
37#include <sys/proc.h>
38#include <sys/counter.h>
39#include <machine/pmc_mdep.h>
40#include <machine/profile.h>
41#ifdef _KERNEL
42#include <sys/epoch.h>
43#include <ck_queue.h>
44#endif
45
46#define PMC_MODULE_NAME "hwpmc"
47#define PMC_NAME_MAX 64 /* HW counter name size */
48#define PMC_CLASS_MAX 8 /* max #classes of PMCs per-system */
49
50/*
51 * Kernel<->userland API version number [MMmmpppp]
52 *
53 * Major numbers are to be incremented when an incompatible change to
54 * the ABI occurs that older clients will not be able to handle.
55 *
56 * Minor numbers are incremented when a backwards compatible change
57 * occurs that allows older correct programs to run unchanged. For
58 * example, when support for a new PMC type is added.
59 *
60 * The patch version is incremented for every bug fix.
61 */
62#define PMC_VERSION_MAJOR 0x0A
63#define PMC_VERSION_MINOR 0x00
64#define PMC_VERSION_PATCH 0x0000
65
66#define PMC_VERSION (PMC_VERSION_MAJOR << 24 | \
67 PMC_VERSION_MINOR << 16 | PMC_VERSION_PATCH)
68
69#define PMC_CPUID_LEN 64
70/* cpu model name for pmu lookup */
71extern char pmc_cpuid[PMC_CPUID_LEN];
72
73/*
74 * Kinds of CPUs known.
75 *
76 * We keep track of CPU variants that need to be distinguished in
77 * some way for PMC operations. CPU names are grouped by manufacturer
78 * and numbered sparsely in order to minimize changes to the ABI involved
79 * when new CPUs are added.
80 *
81 * Please keep the pmc(3) manual page in sync with this list.
82 */
83#define __PMC_CPUS() \
84 __PMC_CPU(AMD_K7, 0x00, "AMD K7") \
85 __PMC_CPU(AMD_K8, 0x01, "AMD K8") \
86 __PMC_CPU(INTEL_CORE, 0x87, "Intel Core Solo/Duo") \
87 __PMC_CPU(INTEL_CORE2, 0x88, "Intel Core2") \
88 __PMC_CPU(INTEL_CORE2EXTREME, 0x89, "Intel Core2 Extreme") \
89 __PMC_CPU(INTEL_ATOM, 0x8A, "Intel Atom") \
90 __PMC_CPU(INTEL_COREI7, 0x8B, "Intel Core i7") \
91 __PMC_CPU(INTEL_WESTMERE, 0x8C, "Intel Westmere") \
92 __PMC_CPU(INTEL_SANDYBRIDGE, 0x8D, "Intel Sandy Bridge") \
93 __PMC_CPU(INTEL_IVYBRIDGE, 0x8E, "Intel Ivy Bridge") \
94 __PMC_CPU(INTEL_SANDYBRIDGE_XEON, 0x8F, "Intel Sandy Bridge Xeon") \
95 __PMC_CPU(INTEL_IVYBRIDGE_XEON, 0x90, "Intel Ivy Bridge Xeon") \
96 __PMC_CPU(INTEL_HASWELL, 0x91, "Intel Haswell") \
97 __PMC_CPU(INTEL_ATOM_SILVERMONT, 0x92, "Intel Atom Silvermont") \
98 __PMC_CPU(INTEL_NEHALEM_EX, 0x93, "Intel Nehalem Xeon 7500") \
99 __PMC_CPU(INTEL_WESTMERE_EX, 0x94, "Intel Westmere Xeon E7") \
100 __PMC_CPU(INTEL_HASWELL_XEON, 0x95, "Intel Haswell Xeon E5 v3") \
101 __PMC_CPU(INTEL_BROADWELL, 0x96, "Intel Broadwell") \
102 __PMC_CPU(INTEL_BROADWELL_XEON, 0x97, "Intel Broadwell Xeon") \
103 __PMC_CPU(INTEL_SKYLAKE, 0x98, "Intel Skylake") \
104 __PMC_CPU(INTEL_SKYLAKE_XEON, 0x99, "Intel Skylake Xeon") \
105 __PMC_CPU(INTEL_ATOM_GOLDMONT, 0x9A, "Intel Atom Goldmont") \
106 __PMC_CPU(INTEL_ICELAKE, 0x9B, "Intel Icelake") \
107 __PMC_CPU(INTEL_ICELAKE_XEON, 0x9C, "Intel Icelake Xeon") \
108 __PMC_CPU(INTEL_ALDERLAKE, 0x9D, "Intel Alderlake") \
109 __PMC_CPU(INTEL_ATOM_GOLDMONT_P, 0x9E, "Intel Atom Goldmont Plus") \
110 __PMC_CPU(INTEL_ATOM_TREMONT, 0x9F, "Intel Atom Tremont") \
111 __PMC_CPU(INTEL_XSCALE, 0x100, "Intel XScale") \
112 __PMC_CPU(PPC_7450, 0x300, "PowerPC MPC7450") \
113 __PMC_CPU(PPC_E500, 0x340, "PowerPC e500 Core") \
114 __PMC_CPU(PPC_970, 0x380, "IBM PowerPC 970") \
115 __PMC_CPU(PPC_POWER8, 0x390, "IBM POWER8") \
116 __PMC_CPU(GENERIC, 0x400, "Generic") \
117 __PMC_CPU(ARMV7_CORTEX_A5, 0x500, "ARMv7 Cortex A5") \
118 __PMC_CPU(ARMV7_CORTEX_A7, 0x501, "ARMv7 Cortex A7") \
119 __PMC_CPU(ARMV7_CORTEX_A8, 0x502, "ARMv7 Cortex A8") \
120 __PMC_CPU(ARMV7_CORTEX_A9, 0x503, "ARMv7 Cortex A9") \
121 __PMC_CPU(ARMV7_CORTEX_A15, 0x504, "ARMv7 Cortex A15") \
122 __PMC_CPU(ARMV7_CORTEX_A17, 0x505, "ARMv7 Cortex A17") \
123 __PMC_CPU(ARMV8_CORTEX_A53, 0x600, "ARMv8 Cortex A53") \
124 __PMC_CPU(ARMV8_CORTEX_A57, 0x601, "ARMv8 Cortex A57") \
125 __PMC_CPU(ARMV8_CORTEX_A76, 0x602, "ARMv8 Cortex A76")
126
127enum pmc_cputype {
128#undef __PMC_CPU
129#define __PMC_CPU(S,V,D) PMC_CPU_##S = V,
130 __PMC_CPUS()
131};
132
133#define PMC_CPU_FIRST PMC_CPU_AMD_K7
134#define PMC_CPU_LAST PMC_CPU_ARMV8_CORTEX_A76
135
136/*
137 * Classes of PMCs
138 */
139#define __PMC_CLASSES() \
140 __PMC_CLASS(TSC, 0x00, "CPU Timestamp counter") \
141 __PMC_CLASS(K7, 0x01, "AMD K7 performance counters") \
142 __PMC_CLASS(K8, 0x02, "AMD K8 performance counters") \
143 __PMC_CLASS(IAF, 0x06, "Intel Core2/Atom, fixed function") \
144 __PMC_CLASS(IAP, 0x07, "Intel Core...Atom, programmable") \
145 __PMC_CLASS(UCF, 0x08, "Intel Uncore fixed function") \
146 __PMC_CLASS(UCP, 0x09, "Intel Uncore programmable") \
147 __PMC_CLASS(XSCALE, 0x0A, "Intel XScale counters") \
148 __PMC_CLASS(PPC7450, 0x0D, "Motorola MPC7450 class") \
149 __PMC_CLASS(PPC970, 0x0E, "IBM PowerPC 970 class") \
150 __PMC_CLASS(SOFT, 0x0F, "Software events") \
151 __PMC_CLASS(ARMV7, 0x10, "ARMv7") \
152 __PMC_CLASS(ARMV8, 0x11, "ARMv8") \
153 __PMC_CLASS(E500, 0x13, "Freescale e500 class") \
154 __PMC_CLASS(POWER8, 0x15, "IBM POWER8 class") \
155 __PMC_CLASS(DMC620_PMU_CD2, 0x16, "ARM DMC620 Memory Controller PMU CLKDIV2") \
156 __PMC_CLASS(DMC620_PMU_C, 0x17, "ARM DMC620 Memory Controller PMU CLK") \
157 __PMC_CLASS(CMN600_PMU, 0x18, "Arm CoreLink CMN600 Coherent Mesh Network PMU")
158
159enum pmc_class {
160#undef __PMC_CLASS
161#define __PMC_CLASS(S,V,D) PMC_CLASS_##S = V,
162 __PMC_CLASSES()
163};
164
165#define PMC_CLASS_FIRST PMC_CLASS_TSC
166#define PMC_CLASS_LAST PMC_CLASS_CMN600_PMU
167
168/*
169 * A PMC can be in the following states:
170 *
171 * Hardware states:
172 * DISABLED -- administratively prohibited from being used.
173 * FREE -- HW available for use
174 * Software states:
175 * ALLOCATED -- allocated
176 * STOPPED -- allocated, but not counting events
177 * RUNNING -- allocated, and in operation; 'pm_runcount'
178 * holds the number of CPUs using this PMC at
179 * a given instant
180 * DELETED -- being destroyed
181 */
182
183#define __PMC_HWSTATES() \
184 __PMC_STATE(DISABLED) \
185 __PMC_STATE(FREE)
186
187#define __PMC_SWSTATES() \
188 __PMC_STATE(ALLOCATED) \
189 __PMC_STATE(STOPPED) \
190 __PMC_STATE(RUNNING) \
191 __PMC_STATE(DELETED)
192
193#define __PMC_STATES() \
194 __PMC_HWSTATES() \
195 __PMC_SWSTATES()
196
197enum pmc_state {
198#undef __PMC_STATE
199#define __PMC_STATE(S) PMC_STATE_##S,
200 __PMC_STATES()
201 __PMC_STATE(MAX)
202};
203
204#define PMC_STATE_FIRST PMC_STATE_DISABLED
205#define PMC_STATE_LAST PMC_STATE_DELETED
206
207/*
208 * An allocated PMC may used as a 'global' counter or as a
209 * 'thread-private' one. Each such mode of use can be in either
210 * statistical sampling mode or in counting mode. Thus a PMC in use
211 *
212 * SS i.e., SYSTEM STATISTICAL -- system-wide statistical profiling
213 * SC i.e., SYSTEM COUNTER -- system-wide counting mode
214 * TS i.e., THREAD STATISTICAL -- thread virtual, statistical profiling
215 * TC i.e., THREAD COUNTER -- thread virtual, counting mode
216 *
217 * Statistical profiling modes rely on the PMC periodically delivering
218 * a interrupt to the CPU (when the configured number of events have
219 * been measured), so the PMC must have the ability to generate
220 * interrupts.
221 *
222 * In counting modes, the PMC counts its configured events, with the
223 * value of the PMC being read whenever needed by its owner process.
224 *
225 * The thread specific modes "virtualize" the PMCs -- the PMCs appear
226 * to be thread private and count events only when the profiled thread
227 * actually executes on the CPU.
228 *
229 * The system-wide "global" modes keep the PMCs running all the time
230 * and are used to measure the behaviour of the whole system.
231 */
232
233#define __PMC_MODES() \
234 __PMC_MODE(SS, 0) \
235 __PMC_MODE(SC, 1) \
236 __PMC_MODE(TS, 2) \
237 __PMC_MODE(TC, 3)
238
239enum pmc_mode {
240#undef __PMC_MODE
241#define __PMC_MODE(M,N) PMC_MODE_##M = N,
242 __PMC_MODES()
243};
244
245#define PMC_MODE_FIRST PMC_MODE_SS
246#define PMC_MODE_LAST PMC_MODE_TC
247
248#define PMC_IS_COUNTING_MODE(mode) \
249 ((mode) == PMC_MODE_SC || (mode) == PMC_MODE_TC)
250#define PMC_IS_SYSTEM_MODE(mode) \
251 ((mode) == PMC_MODE_SS || (mode) == PMC_MODE_SC)
252#define PMC_IS_SAMPLING_MODE(mode) \
253 ((mode) == PMC_MODE_SS || (mode) == PMC_MODE_TS)
254#define PMC_IS_VIRTUAL_MODE(mode) \
255 ((mode) == PMC_MODE_TS || (mode) == PMC_MODE_TC)
256
257/*
258 * PMC row disposition
259 */
260
261#define __PMC_DISPOSITIONS(N) \
262 __PMC_DISP(STANDALONE) /* global/disabled counters */ \
263 __PMC_DISP(FREE) /* free/available */ \
264 __PMC_DISP(THREAD) /* thread-virtual PMCs */ \
265 __PMC_DISP(UNKNOWN) /* sentinel */
266
267enum pmc_disp {
268#undef __PMC_DISP
269#define __PMC_DISP(D) PMC_DISP_##D ,
270 __PMC_DISPOSITIONS()
271};
272
273#define PMC_DISP_FIRST PMC_DISP_STANDALONE
274#define PMC_DISP_LAST PMC_DISP_THREAD
275
276/*
277 * Counter capabilities
278 *
279 * __PMC_CAPS(NAME, VALUE, DESCRIPTION)
280 */
281
282#define __PMC_CAPS() \
283 __PMC_CAP(INTERRUPT, 0, "generate interrupts") \
284 __PMC_CAP(USER, 1, "count user-mode events") \
285 __PMC_CAP(SYSTEM, 2, "count system-mode events") \
286 __PMC_CAP(EDGE, 3, "do edge detection of events") \
287 __PMC_CAP(THRESHOLD, 4, "ignore events below a threshold") \
288 __PMC_CAP(READ, 5, "read PMC counter") \
289 __PMC_CAP(WRITE, 6, "reprogram PMC counter") \
290 __PMC_CAP(INVERT, 7, "invert comparison sense") \
291 __PMC_CAP(QUALIFIER, 8, "further qualify monitored events") \
292 __PMC_CAP(PRECISE, 9, "perform precise sampling") \
293 __PMC_CAP(TAGGING, 10, "tag upstream events") \
294 __PMC_CAP(CASCADE, 11, "cascade counters") \
295 __PMC_CAP(SYSWIDE, 12, "system wide counter") \
296 __PMC_CAP(DOMWIDE, 13, "NUMA domain wide counter")
297
298enum pmc_caps
299{
300#undef __PMC_CAP
301#define __PMC_CAP(NAME, VALUE, DESCR) PMC_CAP_##NAME = (1 << VALUE) ,
302 __PMC_CAPS()
303};
304
305#define PMC_CAP_FIRST PMC_CAP_INTERRUPT
306#define PMC_CAP_LAST PMC_CAP_DOMWIDE
307
308/*
309 * PMC Event Numbers
310 *
311 * These are generated from the definitions in "dev/hwpmc/pmc_events.h".
312 */
313
314enum pmc_event {
315#undef __PMC_EV
316#undef __PMC_EV_BLOCK
317#define __PMC_EV_BLOCK(C,V) PMC_EV_ ## C ## __BLOCK_START = (V) - 1 ,
318#define __PMC_EV(C,N) PMC_EV_ ## C ## _ ## N ,
319 __PMC_EVENTS()
320};
321
322/*
323 * PMC SYSCALL INTERFACE
324 */
325
326/*
327 * "PMC_OPS" -- these are the commands recognized by the kernel
328 * module, and are used when performing a system call from userland.
329 */
330#define __PMC_OPS() \
331 __PMC_OP(CONFIGURELOG, "Set log file") \
332 __PMC_OP(FLUSHLOG, "Flush log file") \
333 __PMC_OP(GETCPUINFO, "Get system CPU information") \
334 __PMC_OP(GETDRIVERSTATS, "Get driver statistics") \
335 __PMC_OP(GETMODULEVERSION, "Get module version") \
336 __PMC_OP(GETPMCINFO, "Get per-cpu PMC information") \
337 __PMC_OP(PMCADMIN, "Set PMC state") \
338 __PMC_OP(PMCALLOCATE, "Allocate and configure a PMC") \
339 __PMC_OP(PMCATTACH, "Attach a PMC to a process") \
340 __PMC_OP(PMCDETACH, "Detach a PMC from a process") \
341 __PMC_OP(PMCGETMSR, "Get a PMC's hardware address") \
342 __PMC_OP(PMCRELEASE, "Release a PMC") \
343 __PMC_OP(PMCRW, "Read/Set a PMC") \
344 __PMC_OP(PMCSETCOUNT, "Set initial count/sampling rate") \
345 __PMC_OP(PMCSTART, "Start a PMC") \
346 __PMC_OP(PMCSTOP, "Stop a PMC") \
347 __PMC_OP(WRITELOG, "Write a cookie to the log file") \
348 __PMC_OP(CLOSELOG, "Close log file") \
349 __PMC_OP(GETDYNEVENTINFO, "Get dynamic events list")
350
351enum pmc_ops {
352#undef __PMC_OP
353#define __PMC_OP(N, D) PMC_OP_##N,
354 __PMC_OPS()
355};
356
357/*
358 * Flags used in operations on PMCs.
359 */
360
361#define PMC_F_UNUSED1 0x00000001 /* unused */
362#define PMC_F_DESCENDANTS 0x00000002 /*OP ALLOCATE track descendants */
363#define PMC_F_LOG_PROCCSW 0x00000004 /*OP ALLOCATE track ctx switches */
364#define PMC_F_LOG_PROCEXIT 0x00000008 /*OP ALLOCATE log proc exits */
365#define PMC_F_NEWVALUE 0x00000010 /*OP RW write new value */
366#define PMC_F_OLDVALUE 0x00000020 /*OP RW get old value */
367
368/* V2 API */
369#define PMC_F_CALLCHAIN 0x00000080 /*OP ALLOCATE capture callchains */
370#define PMC_F_USERCALLCHAIN 0x00000100 /*OP ALLOCATE use userspace stack */
371
372/* V10 API */
373#define PMC_F_EV_PMU 0x00000200 /*
374 * OP ALLOCATE: pm_ev has special
375 * userspace meaning; counter
376 * configuration is communicated
377 * through class-dependent fields
378 */
379
380/* internal flags */
381#define PMC_F_ATTACHED_TO_OWNER 0x00010000 /*attached to owner*/
382#define PMC_F_NEEDS_LOGFILE 0x00020000 /*needs log file */
383#define PMC_F_ATTACH_DONE 0x00040000 /*attached at least once */
384
385#define PMC_CALLCHAIN_DEPTH_MAX 512
386
387#define PMC_CC_F_USERSPACE 0x01 /*userspace callchain*/
388
389/*
390 * Cookies used to denote allocated PMCs, and the values of PMCs.
391 */
392
393typedef uint32_t pmc_id_t;
394typedef uint64_t pmc_value_t;
395
396#define PMC_ID_INVALID (~ (pmc_id_t) 0)
397
398/*
399 * PMC IDs have the following format:
400 *
401 * +-----------------------+-------+-----------+
402 * | CPU | PMC MODE | CLASS | ROW INDEX |
403 * +-----------------------+-------+-----------+
404 *
405 * where CPU is 12 bits, MODE 4, CLASS 8, and ROW INDEX 8 Field 'CPU'
406 * is set to the requested CPU for system-wide PMCs or PMC_CPU_ANY for
407 * process-mode PMCs. Field 'PMC MODE' is the allocated PMC mode.
408 * Field 'PMC CLASS' is the class of the PMC. Field 'ROW INDEX' is the
409 * row index for the PMC.
410 *
411 * The 'ROW INDEX' ranges over 0..NWPMCS where NHWPMCS is the total
412 * number of hardware PMCs on this cpu.
413 */
414
415#define PMC_ID_TO_ROWINDEX(ID) ((ID) & 0xFF)
416#define PMC_ID_TO_CLASS(ID) (((ID) & 0xFF00) >> 8)
417#define PMC_ID_TO_MODE(ID) (((ID) & 0xF0000) >> 16)
418#define PMC_ID_TO_CPU(ID) (((ID) & 0xFFF00000) >> 20)
419#define PMC_ID_MAKE_ID(CPU,MODE,CLASS,ROWINDEX) \
420 ((((CPU) & 0xFFF) << 20) | (((MODE) & 0xF) << 16) | \
421 (((CLASS) & 0xFF) << 8) | ((ROWINDEX) & 0xFF))
422
423/*
424 * Data structures for system calls supported by the pmc driver.
425 */
426
427/*
428 * OP PMCALLOCATE
429 *
430 * Allocate a PMC on the named CPU.
431 */
432
433#define PMC_CPU_ANY ~0
434
435struct pmc_op_pmcallocate {
436 uint32_t pm_caps; /* PMC_CAP_* */
437 uint32_t pm_cpu; /* CPU number or PMC_CPU_ANY */
438 enum pmc_class pm_class; /* class of PMC desired */
439 enum pmc_event pm_ev; /* [enum pmc_event] desired */
440 uint32_t pm_flags; /* additional modifiers PMC_F_* */
441 enum pmc_mode pm_mode; /* desired mode */
442 pmc_id_t pm_pmcid; /* [return] process pmc id */
443 pmc_value_t pm_count; /* initial/sample count */
444
445 union pmc_md_op_pmcallocate pm_md; /* MD layer extensions */
446};
447
448/*
449 * OP PMCADMIN
450 *
451 * Set the administrative state (i.e., whether enabled or disabled) of
452 * a PMC 'pm_pmc' on CPU 'pm_cpu'. Note that 'pm_pmc' specifies an
453 * absolute PMC number and need not have been first allocated by the
454 * calling process.
455 */
456
457struct pmc_op_pmcadmin {
458 int pm_cpu; /* CPU# */
459 uint32_t pm_flags; /* flags */
460 int pm_pmc; /* PMC# */
461 enum pmc_state pm_state; /* desired state */
462};
463
464/*
465 * OP PMCATTACH / OP PMCDETACH
466 *
467 * Attach/detach a PMC and a process.
468 */
469
470struct pmc_op_pmcattach {
471 pmc_id_t pm_pmc; /* PMC to attach to */
472 pid_t pm_pid; /* target process */
473};
474
475/*
476 * OP PMCSETCOUNT
477 *
478 * Set the sampling rate (i.e., the reload count) for statistical counters.
479 * 'pm_pmcid' need to have been previously allocated using PMCALLOCATE.
480 */
481
482struct pmc_op_pmcsetcount {
483 pmc_value_t pm_count; /* initial/sample count */
484 pmc_id_t pm_pmcid; /* PMC id to set */
485};
486
487/*
488 * OP PMCRW
489 *
490 * Read the value of a PMC named by 'pm_pmcid'. 'pm_pmcid' needs
491 * to have been previously allocated using PMCALLOCATE.
492 */
493
494struct pmc_op_pmcrw {
495 uint32_t pm_flags; /* PMC_F_{OLD,NEW}VALUE*/
496 pmc_id_t pm_pmcid; /* pmc id */
497 pmc_value_t pm_value; /* new&returned value */
498};
499
500/*
501 * OP GETPMCINFO
502 *
503 * retrieve PMC state for a named CPU. The caller is expected to
504 * allocate 'npmc' * 'struct pmc_info' bytes of space for the return
505 * values.
506 */
507
508struct pmc_info {
509 char pm_name[PMC_NAME_MAX]; /* pmc name */
510 enum pmc_class pm_class; /* enum pmc_class */
511 int pm_enabled; /* whether enabled */
512 enum pmc_disp pm_rowdisp; /* FREE, THREAD or STANDLONE */
513 pid_t pm_ownerpid; /* owner, or -1 */
514 enum pmc_mode pm_mode; /* current mode [enum pmc_mode] */
515 enum pmc_event pm_event; /* current event */
516 uint32_t pm_flags; /* current flags */
517 pmc_value_t pm_reloadcount; /* sampling counters only */
518};
519
520struct pmc_op_getpmcinfo {
521 int32_t pm_cpu; /* 0 <= cpu < mp_maxid */
522 struct pmc_info pm_pmcs[]; /* space for 'npmc' structures */
523};
524
525/*
526 * OP GETCPUINFO
527 *
528 * Retrieve system CPU information.
529 */
530
531struct pmc_classinfo {
532 enum pmc_class pm_class; /* class id */
533 uint32_t pm_caps; /* counter capabilities */
534 uint32_t pm_width; /* width of the PMC */
535 uint32_t pm_num; /* number of PMCs in class */
536};
537
538struct pmc_op_getcpuinfo {
539 enum pmc_cputype pm_cputype; /* what kind of CPU */
540 uint32_t pm_ncpu; /* max CPU number */
541 uint32_t pm_npmc; /* #PMCs per CPU */
542 uint32_t pm_nclass; /* #classes of PMCs */
543 struct pmc_classinfo pm_classes[PMC_CLASS_MAX];
544};
545
546/*
547 * OP CONFIGURELOG
548 *
549 * Configure a log file for writing system-wide statistics to.
550 */
551
552struct pmc_op_configurelog {
553 int pm_flags;
554 int pm_logfd; /* logfile fd (or -1) */
555};
556
557/*
558 * OP GETDRIVERSTATS
559 *
560 * Retrieve pmc(4) driver-wide statistics.
561 */
562#ifdef _KERNEL
563struct pmc_driverstats {
564 counter_u64_t pm_intr_ignored; /* #interrupts ignored */
565 counter_u64_t pm_intr_processed; /* #interrupts processed */
566 counter_u64_t pm_intr_bufferfull; /* #interrupts with ENOSPC */
567 counter_u64_t pm_syscalls; /* #syscalls */
568 counter_u64_t pm_syscall_errors; /* #syscalls with errors */
569 counter_u64_t pm_buffer_requests; /* #buffer requests */
570 counter_u64_t pm_buffer_requests_failed; /* #failed buffer requests */
571 counter_u64_t pm_log_sweeps; /* #sample buffer processing
572 passes */
573 counter_u64_t pm_merges; /* merged k+u */
574 counter_u64_t pm_overwrites; /* UR overwrites */
575};
576#endif
577
578struct pmc_op_getdriverstats {
579 unsigned int pm_intr_ignored; /* #interrupts ignored */
580 unsigned int pm_intr_processed; /* #interrupts processed */
581 unsigned int pm_intr_bufferfull; /* #interrupts with ENOSPC */
582 unsigned int pm_syscalls; /* #syscalls */
583 unsigned int pm_syscall_errors; /* #syscalls with errors */
584 unsigned int pm_buffer_requests; /* #buffer requests */
585 unsigned int pm_buffer_requests_failed; /* #failed buffer requests */
586 unsigned int pm_log_sweeps; /* #sample buffer processing
587 passes */
588};
589
590/*
591 * OP RELEASE / OP START / OP STOP
592 *
593 * Simple operations on a PMC id.
594 */
595
596struct pmc_op_simple {
597 pmc_id_t pm_pmcid;
598};
599
600/*
601 * OP WRITELOG
602 *
603 * Flush the current log buffer and write 4 bytes of user data to it.
604 */
605
606struct pmc_op_writelog {
607 uint32_t pm_userdata;
608};
609
610/*
611 * OP GETMSR
612 *
613 * Retrieve the machine specific address associated with the allocated
614 * PMC. This number can be used subsequently with a read-performance-counter
615 * instruction.
616 */
617
618struct pmc_op_getmsr {
619 uint32_t pm_msr; /* machine specific address */
620 pmc_id_t pm_pmcid; /* allocated pmc id */
621};
622
623/*
624 * OP GETDYNEVENTINFO
625 *
626 * Retrieve a PMC dynamic class events list.
627 */
628
629struct pmc_dyn_event_descr {
630 char pm_ev_name[PMC_NAME_MAX];
631 enum pmc_event pm_ev_code;
632};
633
634struct pmc_op_getdyneventinfo {
635 enum pmc_class pm_class;
636 unsigned int pm_nevent;
637 struct pmc_dyn_event_descr pm_events[PMC_EV_DYN_COUNT];
638};
639
640#ifdef _KERNEL
641
642#include <sys/malloc.h>
643#include <sys/sysctl.h>
644#include <sys/_cpuset.h>
645
646#include <machine/frame.h>
647
648#define PMC_HASH_SIZE 1024
649#define PMC_MTXPOOL_SIZE 2048
650#define PMC_LOG_BUFFER_SIZE 256
651#define PMC_NLOGBUFFERS_PCPU 32
652#define PMC_NSAMPLES 256
653#define PMC_CALLCHAIN_DEPTH 128
654#define PMC_THREADLIST_MAX 128
655
656#define PMC_SYSCTL_NAME_PREFIX "kern." PMC_MODULE_NAME "."
657
658/*
659 * Locking keys
660 *
661 * (b) - pmc_bufferlist_mtx (spin lock)
662 * (k) - pmc_kthread_mtx (sleep lock)
663 * (o) - po->po_mtx (spin lock)
664 * (g) - global_epoch_preempt (epoch)
665 * (p) - pmc_sx (sx)
666 */
667
668/*
669 * PMC commands
670 */
671
672struct pmc_syscall_args {
673 register_t pmop_code; /* one of PMC_OP_* */
674 void *pmop_data; /* syscall parameter */
675};
676
677/*
678 * Interface to processor specific s1tuff
679 */
680
681/*
682 * struct pmc_descr
683 *
684 * Machine independent (i.e., the common parts) of a human readable
685 * PMC description.
686 */
687
688struct pmc_descr {
689 char pd_name[PMC_NAME_MAX]; /* name */
690 uint32_t pd_caps; /* capabilities */
691 enum pmc_class pd_class; /* class of the PMC */
692 uint32_t pd_width; /* width in bits */
693};
694
695/*
696 * struct pmc_target
697 *
698 * This structure records all the target processes associated with a
699 * PMC.
700 */
701
702struct pmc_target {
703 LIST_ENTRY(pmc_target) pt_next;
704 struct pmc_process *pt_process; /* target descriptor */
705};
706
707/*
708 * struct pmc
709 *
710 * Describes each allocated PMC.
711 *
712 * Each PMC has precisely one owner, namely the process that allocated
713 * the PMC.
714 *
715 * A PMC may be attached to multiple target processes. The
716 * 'pm_targets' field links all the target processes being monitored
717 * by this PMC.
718 *
719 * The 'pm_savedvalue' field is protected by a mutex.
720 *
721 * On a multi-cpu machine, multiple target threads associated with a
722 * process-virtual PMC could be concurrently executing on different
723 * CPUs. The 'pm_runcount' field is atomically incremented every time
724 * the PMC gets scheduled on a CPU and atomically decremented when it
725 * get descheduled. Deletion of a PMC is only permitted when this
726 * field is '0'.
727 *
728 */
729struct pmc_pcpu_state {
730 uint32_t pps_overflowcnt; /* count overflow interrupts */
731 uint8_t pps_stalled;
732 uint8_t pps_cpustate;
733} __aligned(CACHE_LINE_SIZE);
734struct pmc {
735 LIST_HEAD(,pmc_target) pm_targets; /* list of target processes */
736 LIST_ENTRY(pmc) pm_next; /* owner's list */
737
738 /*
739 * System-wide PMCs are allocated on a CPU and are not moved
740 * around. For system-wide PMCs we record the CPU the PMC was
741 * allocated on in the 'CPU' field of the pmc ID.
742 *
743 * Virtual PMCs run on whichever CPU is currently executing
744 * their targets' threads. For these PMCs we need to save
745 * their current PMC counter values when they are taken off
746 * CPU.
747 */
748
749 union {
750 pmc_value_t pm_savedvalue; /* Virtual PMCS */
751 } pm_gv;
752
753 /*
754 * For sampling mode PMCs, we keep track of the PMC's "reload
755 * count", which is the counter value to be loaded in when
756 * arming the PMC for the next counting session. For counting
757 * modes on PMCs that are read-only (e.g., the x86 TSC), we
758 * keep track of the initial value at the start of
759 * counting-mode operation.
760 */
761
762 union {
763 pmc_value_t pm_reloadcount; /* sampling PMC modes */
764 pmc_value_t pm_initial; /* counting PMC modes */
765 } pm_sc;
766
767 struct pmc_pcpu_state *pm_pcpu_state;
768 volatile cpuset_t pm_cpustate; /* CPUs where PMC should be active */
769 uint32_t pm_caps; /* PMC capabilities */
770 enum pmc_event pm_event; /* event being measured */
771 uint32_t pm_flags; /* additional flags PMC_F_... */
772 struct pmc_owner *pm_owner; /* owner thread state */
773 counter_u64_t pm_runcount; /* #cpus currently on */
774 enum pmc_state pm_state; /* current PMC state */
775
776 /*
777 * The PMC ID field encodes the row-index for the PMC, its
778 * mode, class and the CPU# associated with the PMC.
779 */
780
781 pmc_id_t pm_id; /* allocated PMC id */
782 enum pmc_class pm_class;
783
784 /* md extensions */
785 union pmc_md_pmc pm_md;
786};
787
788/*
789 * Accessor macros for 'struct pmc'
790 */
791
792#define PMC_TO_MODE(P) PMC_ID_TO_MODE((P)->pm_id)
793#define PMC_TO_CLASS(P) PMC_ID_TO_CLASS((P)->pm_id)
794#define PMC_TO_ROWINDEX(P) PMC_ID_TO_ROWINDEX((P)->pm_id)
795#define PMC_TO_CPU(P) PMC_ID_TO_CPU((P)->pm_id)
796
797/*
798 * struct pmc_threadpmcstate
799 *
800 * Record per-PMC, per-thread state.
801 */
802struct pmc_threadpmcstate {
803 pmc_value_t pt_pmcval; /* per-thread reload count */
804};
805
806/*
807 * struct pmc_thread
808 *
809 * Record a 'target' thread being profiled.
810 */
811struct pmc_thread {
812 LIST_ENTRY(pmc_thread) pt_next; /* linked list */
813 struct thread *pt_td; /* target thread */
814 struct pmc_threadpmcstate pt_pmcs[]; /* per-PMC state */
815};
816
817/*
818 * struct pmc_process
819 *
820 * Record a 'target' process being profiled.
821 *
822 * The target process being profiled could be different from the owner
823 * process which allocated the PMCs. Each target process descriptor
824 * is associated with NHWPMC 'struct pmc *' pointers. Each PMC at a
825 * given hardware row-index 'n' will use slot 'n' of the 'pp_pmcs[]'
826 * array. The size of this structure is thus PMC architecture
827 * dependent.
828 *
829 */
830
831struct pmc_targetstate {
832 struct pmc *pp_pmc; /* target PMC */
833 pmc_value_t pp_pmcval; /* per-process value */
834};
835
836struct pmc_process {
837 LIST_ENTRY(pmc_process) pp_next; /* hash chain */
838 LIST_HEAD(,pmc_thread) pp_tds; /* list of threads */
839 struct mtx *pp_tdslock; /* lock on pp_tds thread list */
840 int pp_refcnt; /* reference count */
841 uint32_t pp_flags; /* flags PMC_PP_* */
842 struct proc *pp_proc; /* target process */
843 struct pmc_targetstate pp_pmcs[]; /* NHWPMCs */
844};
845
846#define PMC_PP_ENABLE_MSR_ACCESS 0x00000001
847
848/*
849 * struct pmc_owner
850 *
851 * We associate a PMC with an 'owner' process.
852 *
853 * A process can be associated with 0..NCPUS*NHWPMC PMCs during its
854 * lifetime, where NCPUS is the numbers of CPUS in the system and
855 * NHWPMC is the number of hardware PMCs per CPU. These are
856 * maintained in the list headed by the 'po_pmcs' to save on space.
857 *
858 */
859
860struct pmc_owner {
861 LIST_ENTRY(pmc_owner) po_next; /* hash chain */
862 CK_LIST_ENTRY(pmc_owner) po_ssnext; /* (g/p) list of SS PMC owners */
863 LIST_HEAD(, pmc) po_pmcs; /* owned PMC list */
864 TAILQ_HEAD(, pmclog_buffer) po_logbuffers; /* (o) logbuffer list */
865 struct mtx po_mtx; /* spin lock for (o) */
866 struct proc *po_owner; /* owner proc */
867 uint32_t po_flags; /* (k) flags PMC_PO_* */
868 struct proc *po_kthread; /* (k) helper kthread */
869 struct file *po_file; /* file reference */
870 int po_error; /* recorded error */
871 short po_sscount; /* # SS PMCs owned */
872 short po_logprocmaps; /* global mappings done */
873 struct pmclog_buffer *po_curbuf[MAXCPU]; /* current log buffer */
874};
875
876#define PMC_PO_OWNS_LOGFILE 0x00000001 /* has a log file */
877#define PMC_PO_SHUTDOWN 0x00000010 /* in the process of shutdown */
878#define PMC_PO_INITIAL_MAPPINGS_DONE 0x00000020
879
880/*
881 * struct pmc_hw -- describe the state of the PMC hardware
882 *
883 * When in use, a HW PMC is associated with one allocated 'struct pmc'
884 * pointed to by field 'phw_pmc'. When inactive, this field is NULL.
885 *
886 * On an SMP box, one or more HW PMC's in process virtual mode with
887 * the same 'phw_pmc' could be executing on different CPUs. In order
888 * to handle this case correctly, we need to ensure that only
889 * incremental counts get added to the saved value in the associated
890 * 'struct pmc'. The 'phw_save' field is used to keep the saved PMC
891 * value at the time the hardware is started during this context
892 * switch (i.e., the difference between the new (hardware) count and
893 * the saved count is atomically added to the count field in 'struct
894 * pmc' at context switch time).
895 *
896 */
897
898struct pmc_hw {
899 uint32_t phw_state; /* see PHW_* macros below */
900 struct pmc *phw_pmc; /* current thread PMC */
901};
902
903#define PMC_PHW_RI_MASK 0x000000FF
904#define PMC_PHW_CPU_SHIFT 8
905#define PMC_PHW_CPU_MASK 0x0000FF00
906#define PMC_PHW_FLAGS_SHIFT 16
907#define PMC_PHW_FLAGS_MASK 0xFFFF0000
908
909#define PMC_PHW_INDEX_TO_STATE(ri) ((ri) & PMC_PHW_RI_MASK)
910#define PMC_PHW_STATE_TO_INDEX(state) ((state) & PMC_PHW_RI_MASK)
911#define PMC_PHW_CPU_TO_STATE(cpu) (((cpu) << PMC_PHW_CPU_SHIFT) & \
912 PMC_PHW_CPU_MASK)
913#define PMC_PHW_STATE_TO_CPU(state) (((state) & PMC_PHW_CPU_MASK) >> \
914 PMC_PHW_CPU_SHIFT)
915#define PMC_PHW_FLAGS_TO_STATE(flags) (((flags) << PMC_PHW_FLAGS_SHIFT) & \
916 PMC_PHW_FLAGS_MASK)
917#define PMC_PHW_STATE_TO_FLAGS(state) (((state) & PMC_PHW_FLAGS_MASK) >> \
918 PMC_PHW_FLAGS_SHIFT)
919#define PMC_PHW_FLAG_IS_ENABLED (PMC_PHW_FLAGS_TO_STATE(0x01))
920#define PMC_PHW_FLAG_IS_SHAREABLE (PMC_PHW_FLAGS_TO_STATE(0x02))
921
922/*
923 * struct pmc_sample
924 *
925 * Space for N (tunable) PC samples and associated control data.
926 */
927
928struct pmc_sample {
929 uint16_t ps_nsamples; /* callchain depth */
930 uint16_t ps_nsamples_actual;
931 uint16_t ps_cpu; /* cpu number */
932 uint16_t ps_flags; /* other flags */
933 lwpid_t ps_tid; /* thread id */
934 pid_t ps_pid; /* process PID or -1 */
935 int ps_ticks; /* ticks at sample time */
936 /* pad */
937 struct thread *ps_td; /* which thread */
938 struct pmc *ps_pmc; /* interrupting PMC */
939 uintptr_t *ps_pc; /* (const) callchain start */
940 uint64_t ps_tsc; /* tsc value */
941};
942
943#define PMC_SAMPLE_FREE ((uint16_t) 0)
944#define PMC_USER_CALLCHAIN_PENDING ((uint16_t) 0xFFFF)
945
946struct pmc_samplebuffer {
947 volatile uint64_t ps_prodidx; /* producer index */
948 volatile uint64_t ps_considx; /* consumer index */
949 uintptr_t *ps_callchains; /* all saved call chains */
950 struct pmc_sample ps_samples[]; /* array of sample entries */
951};
952
953#define PMC_CONS_SAMPLE(psb) \
954 (&(psb)->ps_samples[(psb)->ps_considx & pmc_sample_mask])
955
956#define PMC_CONS_SAMPLE_OFF(psb, off) \
957 (&(psb)->ps_samples[(off) & pmc_sample_mask])
958
959#define PMC_PROD_SAMPLE(psb) \
960 (&(psb)->ps_samples[(psb)->ps_prodidx & pmc_sample_mask])
961
962/*
963 * struct pmc_cpustate
964 *
965 * A CPU is modelled as a collection of HW PMCs with space for additional
966 * flags.
967 */
968
969struct pmc_cpu {
970 uint32_t pc_state; /* physical cpu number + flags */
971 struct pmc_samplebuffer *pc_sb[3]; /* space for samples */
972 struct pmc_hw *pc_hwpmcs[]; /* 'npmc' pointers */
973};
974
975#define PMC_PCPU_CPU_MASK 0x000000FF
976#define PMC_PCPU_FLAGS_MASK 0xFFFFFF00
977#define PMC_PCPU_FLAGS_SHIFT 8
978#define PMC_PCPU_STATE_TO_CPU(S) ((S) & PMC_PCPU_CPU_MASK)
979#define PMC_PCPU_STATE_TO_FLAGS(S) (((S) & PMC_PCPU_FLAGS_MASK) >> PMC_PCPU_FLAGS_SHIFT)
980#define PMC_PCPU_FLAGS_TO_STATE(F) (((F) << PMC_PCPU_FLAGS_SHIFT) & PMC_PCPU_FLAGS_MASK)
981#define PMC_PCPU_CPU_TO_STATE(C) ((C) & PMC_PCPU_CPU_MASK)
982#define PMC_PCPU_FLAG_HTT (PMC_PCPU_FLAGS_TO_STATE(0x1))
983
984/*
985 * struct pmc_binding
986 *
987 * CPU binding information.
988 */
989
990struct pmc_binding {
991 int pb_bound; /* is bound? */
992 int pb_cpu; /* if so, to which CPU */
993 u_char pb_priority; /* Thread active priority. */
994};
995
996struct pmc_mdep;
997
998/*
999 * struct pmc_classdep
1000 *
1001 * PMC class-dependent operations.
1002 */
1003struct pmc_classdep {
1004 uint32_t pcd_caps; /* class capabilities */
1005 enum pmc_class pcd_class; /* class id */
1006 int pcd_num; /* number of PMCs */
1007 int pcd_ri; /* row index of the first PMC in class */
1008 int pcd_width; /* width of the PMC */
1009
1010 /* configuring/reading/writing the hardware PMCs */
1011 int (*pcd_config_pmc)(int _cpu, int _ri, struct pmc *_pm);
1012 int (*pcd_get_config)(int _cpu, int _ri, struct pmc **_ppm);
1013 int (*pcd_read_pmc)(int _cpu, int _ri, struct pmc *_pm,
1014 pmc_value_t *_value);
1015 int (*pcd_write_pmc)(int _cpu, int _ri, struct pmc *_pm,
1016 pmc_value_t _value);
1017
1018 /* pmc allocation/release */
1019 int (*pcd_allocate_pmc)(int _cpu, int _ri, struct pmc *_t,
1020 const struct pmc_op_pmcallocate *_a);
1021 int (*pcd_release_pmc)(int _cpu, int _ri, struct pmc *_pm);
1022
1023 /* starting and stopping PMCs */
1024 int (*pcd_start_pmc)(int _cpu, int _ri, struct pmc *_pm);
1025 int (*pcd_stop_pmc)(int _cpu, int _ri, struct pmc *_pm);
1026
1027 /* description */
1028 int (*pcd_describe)(int _cpu, int _ri, struct pmc_info *_pi,
1029 struct pmc **_ppmc);
1030
1031 /* class-dependent initialization & finalization */
1032 int (*pcd_pcpu_init)(struct pmc_mdep *_md, int _cpu);
1033 int (*pcd_pcpu_fini)(struct pmc_mdep *_md, int _cpu);
1034
1035 /* machine-specific interface */
1036 int (*pcd_get_msr)(int _ri, uint32_t *_msr);
1037};
1038
1039/*
1040 * struct pmc_mdep
1041 *
1042 * Machine dependent bits needed per CPU type.
1043 */
1044
1045struct pmc_mdep {
1046 uint32_t pmd_cputype; /* from enum pmc_cputype */
1047 uint32_t pmd_npmc; /* number of PMCs per CPU */
1048 uint32_t pmd_nclass; /* number of PMC classes present */
1049
1050 /*
1051 * Machine dependent methods.
1052 */
1053
1054 /* thread context switch in/out */
1055 int (*pmd_switch_in)(struct pmc_cpu *_p, struct pmc_process *_pp);
1056 int (*pmd_switch_out)(struct pmc_cpu *_p, struct pmc_process *_pp);
1057
1058 /* handle a PMC interrupt */
1059 int (*pmd_intr)(struct trapframe *_tf);
1060
1061 /*
1062 * PMC class dependent information.
1063 */
1064 struct pmc_classdep pmd_classdep[];
1065};
1066
1067/*
1068 * Per-CPU state. This is an array of 'mp_ncpu' pointers
1069 * to struct pmc_cpu descriptors.
1070 */
1071
1072extern struct pmc_cpu **pmc_pcpu;
1073
1074/* driver statistics */
1075extern struct pmc_driverstats pmc_stats;
1076
1077#if defined(HWPMC_DEBUG)
1078
1079/* HWPMC_DEBUG without KTR will compile but is a no-op. */
1080#if !defined(KTR) || !defined(KTR_COMPILE) || ((KTR_COMPILE & KTR_SUBSYS) == 0)
1081#error "HWPMC_DEBUG requires KTR and KTR_COMPILE=KTR_SUBSYS -- see ktr(4)"
1082#endif
1083
1084#include <sys/ktr.h>
1085
1086#define __pmcdbg_used /* unused variable annotation */
1087
1088/*
1089 * Debug flags, major flag groups.
1090 *
1091 * Please keep the DEBUGGING section of the hwpmc(4) man page in sync.
1092 */
1093struct pmc_debugflags {
1094 int pdb_CPU;
1095 int pdb_CSW;
1096 int pdb_LOG;
1097 int pdb_MDP;
1098 int pdb_MOD;
1099 int pdb_OWN;
1100 int pdb_PMC;
1101 int pdb_PRC;
1102 int pdb_SAM;
1103};
1104
1105extern struct pmc_debugflags pmc_debugflags;
1106
1107#define KTR_PMC KTR_SUBSYS
1108
1109#define PMC_DEBUG_STRSIZE 128
1110#define PMC_DEBUG_DEFAULT_FLAGS { 0, 0, 0, 0, 0, 0, 0, 0, 0 }
1111
1112#define PMCDBG0(M, N, L, F) do { \
1113 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \
1114 CTR0(KTR_PMC, #M ":" #N ":" #L ": " F); \
1115} while (0)
1116#define PMCDBG1(M, N, L, F, p1) do { \
1117 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \
1118 CTR1(KTR_PMC, #M ":" #N ":" #L ": " F, p1); \
1119} while (0)
1120#define PMCDBG2(M, N, L, F, p1, p2) do { \
1121 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \
1122 CTR2(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2); \
1123} while (0)
1124#define PMCDBG3(M, N, L, F, p1, p2, p3) do { \
1125 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \
1126 CTR3(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3); \
1127} while (0)
1128#define PMCDBG4(M, N, L, F, p1, p2, p3, p4) do { \
1129 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \
1130 CTR4(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3, p4);\
1131} while (0)
1132#define PMCDBG5(M, N, L, F, p1, p2, p3, p4, p5) do { \
1133 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \
1134 CTR5(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3, p4, \
1135 p5); \
1136} while (0)
1137#define PMCDBG6(M, N, L, F, p1, p2, p3, p4, p5, p6) do { \
1138 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \
1139 CTR6(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3, p4, \
1140 p5, p6); \
1141} while (0)
1142
1143/* Major numbers */
1144#define PMC_DEBUG_MAJ_CPU 0 /* cpu switches */
1145#define PMC_DEBUG_MAJ_CSW 1 /* context switches */
1146#define PMC_DEBUG_MAJ_LOG 2 /* logging */
1147#define PMC_DEBUG_MAJ_MDP 3 /* machine dependent */
1148#define PMC_DEBUG_MAJ_MOD 4 /* misc module infrastructure */
1149#define PMC_DEBUG_MAJ_OWN 5 /* owner */
1150#define PMC_DEBUG_MAJ_PMC 6 /* pmc management */
1151#define PMC_DEBUG_MAJ_PRC 7 /* processes */
1152#define PMC_DEBUG_MAJ_SAM 8 /* sampling */
1153
1154/* Minor numbers */
1155
1156/* Common (8 bits) */
1157#define PMC_DEBUG_MIN_ALL 0 /* allocation */
1158#define PMC_DEBUG_MIN_REL 1 /* release */
1159#define PMC_DEBUG_MIN_OPS 2 /* ops: start, stop, ... */
1160#define PMC_DEBUG_MIN_INI 3 /* init */
1161#define PMC_DEBUG_MIN_FND 4 /* find */
1162
1163/* MODULE */
1164#define PMC_DEBUG_MIN_PMH 14 /* pmc_hook */
1165#define PMC_DEBUG_MIN_PMS 15 /* pmc_syscall */
1166
1167/* OWN */
1168#define PMC_DEBUG_MIN_ORM 8 /* owner remove */
1169#define PMC_DEBUG_MIN_OMR 9 /* owner maybe remove */
1170
1171/* PROCESSES */
1172#define PMC_DEBUG_MIN_TLK 8 /* link target */
1173#define PMC_DEBUG_MIN_TUL 9 /* unlink target */
1174#define PMC_DEBUG_MIN_EXT 10 /* process exit */
1175#define PMC_DEBUG_MIN_EXC 11 /* process exec */
1176#define PMC_DEBUG_MIN_FRK 12 /* process fork */
1177#define PMC_DEBUG_MIN_ATT 13 /* attach/detach */
1178#define PMC_DEBUG_MIN_SIG 14 /* signalling */
1179
1180/* CONTEXT SWITCHES */
1181#define PMC_DEBUG_MIN_SWI 8 /* switch in */
1182#define PMC_DEBUG_MIN_SWO 9 /* switch out */
1183
1184/* PMC */
1185#define PMC_DEBUG_MIN_REG 8 /* pmc register */
1186#define PMC_DEBUG_MIN_ALR 9 /* allocate row */
1187
1188/* MACHINE DEPENDENT LAYER */
1189#define PMC_DEBUG_MIN_REA 8 /* read */
1190#define PMC_DEBUG_MIN_WRI 9 /* write */
1191#define PMC_DEBUG_MIN_CFG 10 /* config */
1192#define PMC_DEBUG_MIN_STA 11 /* start */
1193#define PMC_DEBUG_MIN_STO 12 /* stop */
1194#define PMC_DEBUG_MIN_INT 13 /* interrupts */
1195
1196/* CPU */
1197#define PMC_DEBUG_MIN_BND 8 /* bind */
1198#define PMC_DEBUG_MIN_SEL 9 /* select */
1199
1200/* LOG */
1201#define PMC_DEBUG_MIN_GTB 8 /* get buf */
1202#define PMC_DEBUG_MIN_SIO 9 /* schedule i/o */
1203#define PMC_DEBUG_MIN_FLS 10 /* flush */
1204#define PMC_DEBUG_MIN_SAM 11 /* sample */
1205#define PMC_DEBUG_MIN_CLO 12 /* close */
1206
1207#else
1208#define __pmcdbg_used __unused
1209#define PMCDBG0(M, N, L, F) /* nothing */
1210#define PMCDBG1(M, N, L, F, p1)
1211#define PMCDBG2(M, N, L, F, p1, p2)
1212#define PMCDBG3(M, N, L, F, p1, p2, p3)
1213#define PMCDBG4(M, N, L, F, p1, p2, p3, p4)
1214#define PMCDBG5(M, N, L, F, p1, p2, p3, p4, p5)
1215#define PMCDBG6(M, N, L, F, p1, p2, p3, p4, p5, p6)
1216#endif
1217
1218/* declare a dedicated memory pool */
1219MALLOC_DECLARE(M_PMC);
1220
1221/*
1222 * Functions
1223 */
1224
1225struct pmc_mdep *pmc_md_initialize(void); /* MD init function */
1226void pmc_md_finalize(struct pmc_mdep *_md); /* MD fini function */
1227int pmc_getrowdisp(int _ri);
1228int pmc_process_interrupt(int _ring, struct pmc *_pm, struct trapframe *_tf);
1229int pmc_save_kernel_callchain(uintptr_t *_cc, int _maxsamples,
1230 struct trapframe *_tf);
1231int pmc_save_user_callchain(uintptr_t *_cc, int _maxsamples,
1232 struct trapframe *_tf);
1233void pmc_restore_cpu_binding(struct pmc_binding *pb);
1234void pmc_save_cpu_binding(struct pmc_binding *pb);
1235void pmc_select_cpu(int cpu);
1236struct pmc_mdep *pmc_mdep_alloc(int nclasses);
1237void pmc_mdep_free(struct pmc_mdep *md);
1238uint64_t pmc_rdtsc(void);
1239#endif /* _KERNEL */
1240#endif /* _SYS_PMC_H_ */