master
1/*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 *
28 * $NetBSD: spr.h,v 1.25 2002/08/14 15:38:40 matt Exp $
29 */
30#ifndef _POWERPC_SPR_H_
31#define _POWERPC_SPR_H_
32
33#ifndef _LOCORE
34#define mtspr(reg, val) \
35 __asm __volatile("mtspr %0,%1" : : "K"(reg), "r"(val))
36#define mfspr(reg) \
37 ( { register_t val; \
38 __asm __volatile("mfspr %0,%1" : "=r"(val) : "K"(reg)); \
39 val; } )
40
41#ifndef __powerpc64__
42
43/* The following routines allow manipulation of the full 64-bit width
44 * of SPRs on 64 bit CPUs in bridge mode */
45
46#define mtspr64(reg,valhi,vallo,scratch) \
47 __asm __volatile(" \
48 mfmsr %0; \
49 insrdi %0,%5,1,0; \
50 mtmsrd %0; \
51 isync; \
52 \
53 sld %1,%1,%4; \
54 or %1,%1,%2; \
55 mtspr %3,%1; \
56 srd %1,%1,%4; \
57 \
58 clrldi %0,%0,1; \
59 mtmsrd %0; \
60 isync;" \
61 : "=r"(scratch), "=r"(valhi) : "r"(vallo), "K"(reg), "r"(32), "r"(1))
62
63#define mfspr64upper(reg,scratch) \
64 ( { register_t val; \
65 __asm __volatile(" \
66 mfmsr %0; \
67 insrdi %0,%4,1,0; \
68 mtmsrd %0; \
69 isync; \
70 \
71 mfspr %1,%2; \
72 srd %1,%1,%3; \
73 \
74 clrldi %0,%0,1; \
75 mtmsrd %0; \
76 isync;" \
77 : "=r"(scratch), "=r"(val) : "K"(reg), "r"(32), "r"(1)); \
78 val; } )
79
80#endif
81
82#endif /* _LOCORE */
83
84/*
85 * Special Purpose Register declarations.
86 *
87 * The first column in the comments indicates which PowerPC
88 * architectures the SPR is valid on - 4 for 4xx series,
89 * 6 for 6xx/7xx series and 8 for 8xx and 8xxx series.
90 */
91
92#define SPR_MQ 0x000 /* .6. 601 MQ register */
93#define SPR_XER 0x001 /* 468 Fixed Point Exception Register */
94#define SPR_DSCR 0x003 /* .6. Data Stream Control Register (Unprivileged) */
95#define SPR_RTCU_R 0x004 /* .6. 601 RTC Upper - Read */
96#define SPR_RTCL_R 0x005 /* .6. 601 RTC Lower - Read */
97#define SPR_LR 0x008 /* 468 Link Register */
98#define SPR_CTR 0x009 /* 468 Count Register */
99#define SPR_DSCRP 0x011 /* Data Stream Control Register (Privileged) */
100#define SPR_DSISR 0x012 /* .68 DSI exception source */
101#define DSISR_DIRECT 0x80000000 /* Direct-store error exception */
102#define DSISR_NOTFOUND 0x40000000 /* Translation not found */
103#define DSISR_PROTECT 0x08000000 /* Memory access not permitted */
104#define DSISR_INVRX 0x04000000 /* Reserve-indexed insn direct-store access */
105#define DSISR_STORE 0x02000000 /* Store operation */
106#define DSISR_DABR 0x00400000 /* DABR match */
107#define DSISR_SEGMENT 0x00200000 /* XXX; not in 6xx PEM */
108#define DSISR_EAR 0x00100000 /* eciwx/ecowx && EAR[E] == 0 */
109#define DSISR_MC_UE_DEFERRED 0x00008000 /* UE deferred error */
110#define DSISR_MC_UE_TABLEWALK 0x00004000 /* UE deferred error during tablewalk */
111#define DSISR_MC_DERAT_MULTIHIT 0x00000800 /* D-ERAT multi-hit */
112#define DSISR_MC_TLB_MULTIHIT 0x00000400 /* TLB multi-hit */
113#define DSISR_MC_TLBIE_ERR 0x00000200 /* TLBIE or TLBIEL programming error */
114#define DSISR_MC_SLB_PARITY 0x00000100 /* SLB parity error */
115#define DSISR_MC_SLB_MULTIHIT 0x00000080 /* SLB Multi-hit detected (D-side) */
116#define DSISR_MC_BAD_REAL_LD 0x00000040 /* Bad real address for load. */
117#define DSISR_MC_BAD_ADDR 0x00000020 /* Bad address for load or store tablewalk */
118#define SPR_DAR 0x013 /* .68 Data Address Register */
119#define SPR_RTCU_W 0x014 /* .6. 601 RTC Upper - Write */
120#define SPR_RTCL_W 0x015 /* .6. 601 RTC Lower - Write */
121#define SPR_DEC 0x016 /* .68 DECrementer register */
122#define SPR_SDR1 0x019 /* .68 Page table base address register */
123#define SPR_SRR0 0x01a /* 468 Save/Restore Register 0 */
124#define SPR_SRR1 0x01b /* 468 Save/Restore Register 1 */
125#define SRR1_ISI_PFAULT 0x40000000 /* ISI page not found */
126#define SRR1_ISI_NOEXECUTE 0x10000000 /* Memory marked no-execute */
127#define SRR1_ISI_PP 0x08000000 /* PP bits forbid access */
128#define SRR1_MCHK_DATA 0x00200000 /* Machine check data in DSISR */
129#define SRR1_MCHK_IFETCH_M 0x081c0000 /* Machine check instr fetch mask */
130#define SRR1_MCHK_IFETCH_SLBMH 0x000c0000 /* SLB multihit */
131#define SPR_CFAR 0x01c /* Come From Address Register */
132#define SPR_AMR 0x01d /* Authority Mask Register */
133
134#define SPR_PID 0x030 /* 4.. Process ID */
135
136#define SPR_DECAR 0x036 /* ..8 Decrementer auto reload */
137#define SPR_IAMR 0x03d /* Instr. Authority Mask Reg */
138
139#define SPR_EIE 0x050 /* ..8 Exception Interrupt ??? */
140#define SPR_EID 0x051 /* ..8 Exception Interrupt ??? */
141#define SPR_NRI 0x052 /* ..8 Exception Interrupt ??? */
142#define SPR_FSCR 0x099 /* Facility Status and Control Register */
143#define FSCR_IC_MASK 0xFF00000000000000ULL /* FSCR[0:7] is Interrupt Cause */
144#define FSCR_IC_FP 0x0000000000000000ULL /* FP unavailable */
145#define FSCR_IC_VSX 0x0100000000000000ULL /* VSX unavailable */
146#define FSCR_IC_DSCR 0x0200000000000000ULL /* Access to the DSCR at SPRs 3 or 17 */
147#define FSCR_IC_PM 0x0300000000000000ULL /* Read or write access of a Performance Monitor SPR in group A */
148#define FSCR_IC_BHRB 0x0400000000000000ULL /* Execution of a BHRB Instruction */
149#define FSCR_IC_HTM 0x0500000000000000ULL /* Access to a Transactional Memory */
150/* Reserved 0x0600000000000000ULL */
151#define FSCR_IC_EBB 0x0700000000000000ULL /* Access to Event-Based Branch */
152#define FSCR_IC_TAR 0x0800000000000000ULL /* Access to Target Address Register */
153#define FSCR_IC_STOP 0x0900000000000000ULL /* Access to the 'stop' instruction in privileged non-hypervisor state */
154#define FSCR_IC_MSG 0x0A00000000000000ULL /* Access to 'msgsndp' or 'msgclrp' instructions */
155#define FSCR_IC_LM 0x0A00000000000000ULL /* Access to load monitored facility */
156#define FSCR_IC_SCV 0x0C00000000000000ULL /* Execution of a 'scv' instruction */
157#define FSCR_SCV 0x0000000000001000 /* scv instruction available */
158#define FSCR_LM 0x0000000000000800 /* Load monitored facilities available */
159#define FSCR_MSGP 0x0000000000000400 /* msgsndp and SPRs available */
160#define FSCR_TAR 0x0000000000000100 /* TAR register available */
161#define FSCR_EBB 0x0000000000000080 /* Event-based branch available */
162#define FSCR_DSCR 0x0000000000000004 /* DSCR available in PR state */
163#define SPR_UAMOR 0x09d /* User Authority Mask Override Register */
164#define SPR_DPDES 0x0b0 /* .6. Directed Privileged Doorbell Exception State Register */
165#define SPR_USPRG0 0x100 /* 4.8 User SPR General 0 */
166#define SPR_VRSAVE 0x100 /* .6. AltiVec VRSAVE */
167#define SPR_SPRG0 0x110 /* 468 SPR General 0 */
168#define SPR_SPRG1 0x111 /* 468 SPR General 1 */
169#define SPR_SPRG2 0x112 /* 468 SPR General 2 */
170#define SPR_SPRG3 0x113 /* 468 SPR General 3 */
171#define SPR_SPRG4 0x114 /* 4.8 SPR General 4 */
172#define SPR_SPRG5 0x115 /* 4.8 SPR General 5 */
173#define SPR_SPRG6 0x116 /* 4.8 SPR General 6 */
174#define SPR_SPRG7 0x117 /* 4.8 SPR General 7 */
175#define SPR_SCOMC 0x114 /* ... SCOM Address Register (970) */
176#define SPR_SCOMD 0x115 /* ... SCOM Data Register (970) */
177#define SPR_ASR 0x118 /* ... Address Space Register (PPC64) */
178#define SPR_EAR 0x11a /* .68 External Access Register */
179#define SPR_PVR 0x11f /* 468 Processor Version Register */
180#define MPC601 0x0001
181#define MPC603 0x0003
182#define MPC604 0x0004
183#define MPC602 0x0005
184#define MPC603e 0x0006
185#define MPC603ev 0x0007
186#define MPC750 0x0008
187#define MPC750CL 0x7000 /* Nintendo Wii's Broadway */
188#define MPC604ev 0x0009
189#define MPC7400 0x000c
190#define MPC620 0x0014
191#define IBM403 0x0020
192#define IBM401A1 0x0021
193#define IBM401B2 0x0022
194#define IBM401C2 0x0023
195#define IBM401D2 0x0024
196#define IBM401E2 0x0025
197#define IBM401F2 0x0026
198#define IBM401G2 0x0027
199#define IBMRS64II 0x0033
200#define IBMRS64III 0x0034
201#define IBMPOWER4 0x0035
202#define IBMRS64III_2 0x0036
203#define IBMRS64IV 0x0037
204#define IBMPOWER4PLUS 0x0038
205#define IBM970 0x0039
206#define IBMPOWER5 0x003a
207#define IBMPOWER5PLUS 0x003b
208#define IBM970FX 0x003c
209#define IBMPOWER6 0x003e
210#define IBMPOWER7 0x003f
211#define IBMPOWER3 0x0040
212#define IBMPOWER3PLUS 0x0041
213#define IBM970MP 0x0044
214#define IBM970GX 0x0045
215#define IBMPOWERPCA2 0x0049
216#define IBMPOWER7PLUS 0x004a
217#define IBMPOWER8E 0x004b
218#define IBMPOWER8NVL 0x004c
219#define IBMPOWER8 0x004d
220#define IBMPOWER9 0x004e
221#define MPC860 0x0050
222#define IBMCELLBE 0x0070
223#define IBMPOWER10 0x0080
224#define MPC8240 0x0081
225#define IBMPOWER11 0x0082
226#define PA6T 0x0090
227#define IBM405GP 0x4011
228#define IBM405L 0x4161
229#define IBM750FX 0x7000
230#define MPC745X_P(v) ((v & 0xFFF8) == 0x8000)
231#define MPC7450 0x8000
232#define MPC7455 0x8001
233#define MPC7457 0x8002
234#define MPC7447A 0x8003
235#define MPC7448 0x8004
236#define MPC7410 0x800c
237#define MPC8245 0x8081
238#define FSL_E500v1 0x8020
239#define FSL_E500v2 0x8021
240#define FSL_E500mc 0x8023
241#define FSL_E5500 0x8024
242#define FSL_E6500 0x8040
243#define FSL_E300C1 0x8083
244#define FSL_E300C2 0x8084
245#define FSL_E300C3 0x8085
246#define FSL_E300C4 0x8086
247
248#define LPCR_PECE_WAKESET (LPCR_PECE_EXT | LPCR_PECE_DECR | LPCR_PECE_ME)
249
250#define SPR_DBSR 0x130 /* ..8 Debug Status Register */
251#define DBSR_IDE 0x80000000 /* Imprecise debug event. */
252#define DBSR_UDE 0x40000000 /* Unconditional debug event. */
253#define DBSR_MRR 0x30000000 /* Most recent Reset (mask). */
254#define DBSR_ICMP 0x08000000 /* Instr. complete debug event. */
255#define DBSR_BRT 0x04000000 /* Branch taken debug event. */
256#define DBSR_IRPT 0x02000000 /* Interrupt taken debug event. */
257#define DBSR_TRAP 0x01000000 /* Trap instr. debug event. */
258#define DBSR_IAC1 0x00800000 /* Instr. address compare #1. */
259#define DBSR_IAC2 0x00400000 /* Instr. address compare #2. */
260#define DBSR_IAC3 0x00200000 /* Instr. address compare #3. */
261#define DBSR_IAC4 0x00100000 /* Instr. address compare #4. */
262#define DBSR_DAC1R 0x00080000 /* Data addr. read compare #1. */
263#define DBSR_DAC1W 0x00040000 /* Data addr. write compare #1. */
264#define DBSR_DAC2R 0x00020000 /* Data addr. read compare #2. */
265#define DBSR_DAC2W 0x00010000 /* Data addr. write compare #2. */
266#define DBSR_RET 0x00008000 /* Return debug event. */
267#define SPR_EPCR 0x133
268#define EPCR_EXTGS 0x80000000
269#define EPCR_DTLBGS 0x40000000
270#define EPCR_ITLBGS 0x20000000
271#define EPCR_DSIGS 0x10000000
272#define EPCR_ISIGS 0x08000000
273#define EPCR_DUVGS 0x04000000
274#define EPCR_ICM 0x02000000
275#define EPCR_GICMGS 0x01000000
276#define EPCR_DGTMI 0x00800000
277#define EPCR_DMIUH 0x00400000
278#define EPCR_PMGS 0x00200000
279#define SPR_DBCR0 0x134 /* ..8 Debug Control Register 0 */
280#define SPR_DBCR1 0x135 /* ..8 Debug Control Register 1 */
281#define SPR_DBCR2 0x136 /* ..8 Debug Control Register 2 */
282#define SPR_IAC1 0x138 /* ..8 Instruction Address Compare 1 */
283#define SPR_IAC2 0x139 /* ..8 Instruction Address Compare 2 */
284#define SPR_IAC3 0x13a /* ..8 Instruction Address Compare 3 */
285#define SPR_IAC4 0x13b /* ..8 Instruction Address Compare 4 */
286
287#define SPR_HSRR0 0x13a
288#define SPR_HSRR1 0x13b
289#define SPR_DAC1 0x13c /* ..8 Data Address Compare 1 */
290#define SPR_DAC2 0x13d /* ..8 Data Address Compare 2 */
291#define SPR_DVC1 0x13e /* ..8 Data Value Compare 1 */
292#define SPR_DVC2 0x13f /* ..8 Data Value Compare 2 */
293
294#define SPR_LPCR 0x13e /* .6. Logical Partitioning Control */
295#define LPCR_LPES 0x008 /* Bit 60 */
296#define LPCR_HVICE 0x002 /* Hypervisor Virtualization Interrupt (Arch 3.0) */
297#define LPCR_ILE (1ULL << 25) /* Interrupt Little-Endian (ISA 2.07) */
298#define LPCR_UPRT (1ULL << 22) /* Use Process Table (ISA 3) */
299#define LPCR_HR (1ULL << 20) /* Host Radix mode */
300#define LPCR_PECE_DRBL (1ULL << 16) /* Directed Privileged Doorbell */
301#define LPCR_PECE_HDRBL (1ULL << 15) /* Directed Hypervisor Doorbell */
302#define LPCR_PECE_EXT (1ULL << 14) /* External exceptions */
303#define LPCR_PECE_DECR (1ULL << 13) /* Decrementer exceptions */
304#define LPCR_PECE_ME (1ULL << 12) /* Machine Check and Hypervisor */
305 /* Maintenance exceptions */
306#define SPR_LPID 0x13f /* .6. Logical Partitioning Control */
307#define SPR_HMER 0x150 /* Hypervisor Maintenance Exception Register */
308#define SPR_HMEER 0x151 /* Hypervisor Maintenance Exception Enable Register */
309#define SPR_AMOR 0x15d /* Authority Mask Override Register */
310
311#define SPR_TIR 0x1be /* .6. Thread Identification Register */
312#define SPR_PTCR 0x1d0 /* Partition Table Control Register */
313#define SPR_SPEFSCR 0x200 /* ..8 Signal Processing Engine FSCR. */
314#define SPEFSCR_SOVH 0x80000000
315#define SPEFSCR_OVH 0x40000000
316#define SPEFSCR_FGH 0x20000000
317#define SPEFSCR_FXH 0x10000000
318#define SPEFSCR_FINVH 0x08000000
319#define SPEFSCR_FDBZH 0x04000000
320#define SPEFSCR_FUNFH 0x02000000
321#define SPEFSCR_FOVFH 0x01000000
322#define SPEFSCR_FINXS 0x00200000
323#define SPEFSCR_FINVS 0x00100000
324#define SPEFSCR_FDBZS 0x00080000
325#define SPEFSCR_FUNFS 0x00040000
326#define SPEFSCR_FOVFS 0x00020000
327#define SPEFSCR_SOV 0x00008000
328#define SPEFSCR_OV 0x00004000
329#define SPEFSCR_FG 0x00002000
330#define SPEFSCR_FX 0x00001000
331#define SPEFSCR_FINV 0x00000800
332#define SPEFSCR_FDBZ 0x00000400
333#define SPEFSCR_FUNF 0x00000200
334#define SPEFSCR_FOVF 0x00000100
335#define SPEFSCR_FINXE 0x00000040
336#define SPEFSCR_FINVE 0x00000020
337#define SPEFSCR_FDBZE 0x00000010
338#define SPEFSCR_FUNFE 0x00000008
339#define SPEFSCR_FOVFE 0x00000004
340#define SPEFSCR_FRMC_M 0x00000003
341#define SPEFSCR_DFLT (SPEFSCR_FINVE | SPEFSCR_FDBZE | \
342 SPEFSCR_FUNFE | SPEFSCR_FOVFE)
343#define SPR_IBAT0U 0x210 /* .6. Instruction BAT Reg 0 Upper */
344#define SPR_IBAT0L 0x211 /* .6. Instruction BAT Reg 0 Lower */
345#define SPR_IBAT1U 0x212 /* .6. Instruction BAT Reg 1 Upper */
346#define SPR_IBAT1L 0x213 /* .6. Instruction BAT Reg 1 Lower */
347#define SPR_IBAT2U 0x214 /* .6. Instruction BAT Reg 2 Upper */
348#define SPR_IBAT2L 0x215 /* .6. Instruction BAT Reg 2 Lower */
349#define SPR_IBAT3U 0x216 /* .6. Instruction BAT Reg 3 Upper */
350#define SPR_IBAT3L 0x217 /* .6. Instruction BAT Reg 3 Lower */
351#define SPR_DBAT0U 0x218 /* .6. Data BAT Reg 0 Upper */
352#define SPR_DBAT0L 0x219 /* .6. Data BAT Reg 0 Lower */
353#define SPR_DBAT1U 0x21a /* .6. Data BAT Reg 1 Upper */
354#define SPR_DBAT1L 0x21b /* .6. Data BAT Reg 1 Lower */
355#define SPR_DBAT2U 0x21c /* .6. Data BAT Reg 2 Upper */
356#define SPR_DBAT2L 0x21d /* .6. Data BAT Reg 2 Lower */
357#define SPR_DBAT3U 0x21e /* .6. Data BAT Reg 3 Upper */
358#define SPR_DBAT3L 0x21f /* .6. Data BAT Reg 3 Lower */
359#define SPR_IBAT4U 0x230 /* .6. Instruction BAT Reg 4 Upper */
360#define SPR_DBCR3 0x231 /* ..8 Debug Control Register 3 */
361#define SPR_IBAT4L 0x231 /* .6. Instruction BAT Reg 4 Lower */
362#define SPR_IBAT5U 0x232 /* .6. Instruction BAT Reg 5 Upper */
363#define SPR_IBAT5L 0x233 /* .6. Instruction BAT Reg 5 Lower */
364#define SPR_DBCR4 0x233 /* ..8 Debug Control Register 4 */
365#define SPR_IBAT6U 0x234 /* .6. Instruction BAT Reg 6 Upper */
366#define SPR_DBCR5 0x234 /* ..8 Debug Control Register 5 */
367#define SPR_IBAT6L 0x235 /* .6. Instruction BAT Reg 6 Lower */
368#define SPR_IAC5 0x235 /* ..8 Instruction Address Compare 5 */
369#define SPR_IBAT7U 0x236 /* .6. Instruction BAT Reg 7 Upper */
370#define SPR_IAC6 0x236 /* ..8 Instruction Address Compare 6 */
371#define SPR_IBAT7L 0x237 /* .6. Instruction BAT Reg 7 Lower */
372#define SPR_IAC7 0x237 /* ..8 Instruction Address Compare 7 */
373#define SPR_DBAT4U 0x238 /* .6. Data BAT Reg 4 Upper */
374#define SPR_IAC8 0x238 /* ..8 Instruction Address Compare 8 */
375#define SPR_DBAT4L 0x239 /* .6. Data BAT Reg 4 Lower */
376#define SPR_DBAT5U 0x23a /* .6. Data BAT Reg 5 Upper */
377#define SPR_DBAT5L 0x23b /* .6. Data BAT Reg 5 Lower */
378#define SPR_DBAT6U 0x23c /* .6. Data BAT Reg 6 Upper */
379#define SPR_DBAT6L 0x23d /* .6. Data BAT Reg 6 Lower */
380#define SPR_DBAT7U 0x23e /* .6. Data BAT Reg 7 Upper */
381#define SPR_DBAT7L 0x23f /* .6. Data BAT Reg 7 Lower */
382#define SPR_DBCR6 0x25b /* ..8 Debug Control Register 6 */
383#define SPR_SPRG8 0x25c /* ..8 SPR General 8 */
384
385#define SPR_MMCRA 0x312 /* ... Monitor Mode Control Register A */
386#define SPR_PMC1 0x313 /* ... PMC 1 */
387#define SPR_PMC2 0x314 /* ... PMC 2 */
388#define SPR_PMC3 0x315 /* ... PMC 3 */
389#define SPR_PMC4 0x316 /* ... PMC 4 */
390#define SPR_PMC5 0x317 /* ... PMC 5 */
391#define SPR_PMC6 0x318 /* ... PMC 6 */
392#define SPR_PMC7 0x319 /* ... PMC 7 */
393#define SPR_PMC8 0x31a /* ... PMC 8 */
394
395#define SPR_MMCR0 0x31b /* ... Monitor Mode Control Register 0 */
396#define SPR_MMCR0_FC 0x80000000 /* Freeze counters */
397#define SPR_MMCR0_FCS 0x40000000 /* Freeze counters in supervisor mode */
398#define SPR_MMCR0_FCP 0x20000000 /* Freeze counters in user mode */
399#define SPR_MMCR0_FCM1 0x10000000 /* Freeze counters when mark=1 */
400#define SPR_MMCR0_FCM0 0x08000000 /* Freeze counters when mark=0 */
401#define SPR_MMCR0_PMXE 0x04000000 /* Enable PM interrupt */
402#define SPR_MMCR0_PMAE 0x04000000 /* PM Alert Enable */
403#define SPR_MMCR0_FCECE 0x02000000 /* Freeze counters after event */
404#define SPR_MMCR0_TBSEL_15 0x01800000 /* Count bit 15 of TBL */
405#define SPR_MMCR0_TBSEL_19 0x01000000 /* Count bit 19 of TBL */
406#define SPR_MMCR0_TBSEL_23 0x00800000 /* Count bit 23 of TBL */
407#define SPR_MMCR0_TBSEL_31 0x00000000 /* Count bit 31 of TBL */
408#define SPR_MMCR0_TBEE 0x00400000 /* Time-base event enable */
409#define SPR_MMCR0_THRESHOLD(x) ((x) << 16) /* Threshold value */
410#define SPR_MMCR0_PMC1CE 0x00008000 /* PMC1 condition enable */
411#define SPR_MMCR0_PMCNCE 0x00004000 /* PMCn condition enable */
412#define SPR_MMCR0_TRIGGER 0x00002000 /* Trigger */
413#define SPR_MMCR0_PMAO 0x00000080 /* PM Alert Occurred */
414#define SPR_MMCR0_FCPC 0x00001000 /* Freeze Counters in Problem State Cond. */
415#define SPR_MMCR0_FC56 0x00000010 /* Freeze Counters 5-6 */
416#define SPR_MMCR0_PMC1SEL(x) ((x) << 8) /* PMC1 selector (970) */
417#define SPR_MMCR0_PMC2SEL(x) ((x) << 1) /* PMC2 selector (970) */
418#define SPR_MMCR0_74XX_PMC1SEL(x) (((x) & 0x3f) << 6) /* PMC1 selector */
419#define SPR_MMCR0_74XX_PMC2SEL(x) (((x) & 0x3f) << 0) /* PMC2 selector */
420
421#define SPR_MMCR1 0x31e /* ... Monitor Mode Control Register 1 */
422#define SPR_MMCR1_PMC3SEL(x) (((x) & 0x1f) << 27) /* PMC 3 selector */
423#define SPR_MMCR1_PMC4SEL(x) (((x) & 0x1f) << 22) /* PMC 4 selector */
424#define SPR_MMCR1_PMC5SEL(x) (((x) & 0x1f) << 17) /* PMC 5 selector */
425#define SPR_MMCR1_PMC6SEL(x) (((x) & 0x1f) << 12) /* PMC 6 selector */
426#define SPR_MMCR1_74XX_PMC6SEL(x) (((x) & 0x3f) << 11) /* PMC 6 selector */
427#define SPR_MMCR1_PMC7SEL(x) (((x) & 0x1f) << 7) /* PMC 7 selector */
428#define SPR_MMCR1_PMC8SEL(x) (((x) & 0x1f) << 2) /* PMC 8 selector */
429#define SPR_MMCR1_P8_PMCSEL_ALL 0xffffffff
430#define SPR_MMCR1_P8_PMCNSEL_MASK(n) (0xffUL << ((3-(n))*8))
431#define SPR_MMCR1_P8_PMCNSEL(n, v) ((unsigned long)(v) << ((3-(n))*8))
432
433#define SPR_MMCR2 0x311
434#define SPR_MMCR2_CNBIT(n, bit) ((bit) << (((5 - (n)) * 9) + 10))
435#define SPR_MMCR2_FCNS(n) SPR_MMCR2_CNBIT(n, 0x100ULL)
436#define SPR_MMCR2_FCNP0(n) SPR_MMCR2_CNBIT(n, 0x080ULL)
437#define SPR_MMCR2_FCNP1(n) SPR_MMCR2_CNBIT(n, 0x040ULL)
438#define SPR_MMCR2_FCNM1(n) SPR_MMCR2_CNBIT(n, 0x020ULL)
439#define SPR_MMCR2_FCNM0(n) SPR_MMCR2_CNBIT(n, 0x010ULL)
440#define SPR_MMCR2_FCNWAIT(n) SPR_MMCR2_CNBIT(n, 0x008ULL)
441#define SPR_MMCR2_FCNH(n) SPR_MMCR2_CNBIT(n, 0x004ULL)
442/* Freeze Counter N in Hypervisor/Supervisor/Problem states */
443#define SPR_MMCR2_FCNHSP(n) \
444 (SPR_MMCR2_FCNS(n) | SPR_MMCR2_FCNP0(n) | \
445 SPR_MMCR2_FCNP1(n) | SPR_MMCR2_FCNH(n))
446
447#define SPR_M_TWB 0x31c /* ..8 MMU tablewalk base */
448#define M_TWB_L1TB 0xfffff000 /* level-1 translation base */
449#define M_TWB_L1INDX 0x00000ffc /* level-1 index */
450#define SPR_MD_TWC 0x31d /* ..8 DMMU tablewalk control */
451#define SPR_MD_RPN 0x31e /* ..8 DMMU real (phys) page number */
452#define SPR_MD_TW 0x31f /* ..8 MMU tablewalk scratch */
453#define SPR_BESCRS 0x320 /* .6. Branch Event Status and Control Set Register */
454#define SPR_BESCRSU 0x321 /* .6. Branch Event Status and Control Set Register (upper 32-bit) */
455#define SPR_BESCRR 0x322 /* .6. Branch Event Status and Control Reset Register */
456#define SPR_BESCRRU 0x323 /* .6. Branch Event Status and Control Register (upper 32-bit) */
457#define SPR_EBBHR 0x324 /* .6. Event-based Branch Handler Register */
458#define SPR_EBBRR 0x325 /* .6. Event-based Branch Return Register */
459#define SPR_BESCR 0x326 /* .6. Branch Event Status and Control Register */
460#define SPR_LMRR 0x32d /* .6. Load Monitored Region Register */
461#define SPR_LMSER 0x32e /* .6. Load Monitored Section Enable Register */
462#define SPR_TAR 0x32f /* .6. Branch Target Address Register */
463#define SPR_MI_CAM 0x330 /* ..8 IMMU CAM entry read */
464#define SPR_MI_RAM0 0x331 /* ..8 IMMU RAM entry read reg 0 */
465#define SPR_MI_RAM1 0x332 /* ..8 IMMU RAM entry read reg 1 */
466#define SPR_MD_CAM 0x338 /* ..8 IMMU CAM entry read */
467#define SPR_MD_RAM0 0x339 /* ..8 IMMU RAM entry read reg 0 */
468#define SPR_MD_RAM1 0x33a /* ..8 IMMU RAM entry read reg 1 */
469#define SPR_PSSCR 0x357 /* Processor Stop Status and Control Register (ISA 3.0) */
470#define PSSCR_PLS_S 60
471#define PSSCR_PLS_M (0xf << PSSCR_PLS_S)
472#define PSSCR_SD (1 << 22)
473#define PSSCR_ESL (1 << 21)
474#define PSSCR_EC (1 << 20)
475#define PSSCR_PSLL_S 16
476#define PSSCR_PSLL_M (0xf << PSSCR_PSLL_S)
477#define PSSCR_TR_S 8
478#define PSSCR_TR_M (0x3 << PSSCR_TR_S)
479#define PSSCR_MTL_S 4
480#define PSSCR_MTL_M (0xf << PSSCR_MTL_S)
481#define PSSCR_RL_S 0
482#define PSSCR_RL_M (0xf << PSSCR_RL_S)
483#define SPR_PMCR 0x374 /* Processor Management Control Register */
484#define SPR_UMMCR2 0x3a0 /* .6. User Monitor Mode Control Register 2 */
485#define SPR_UMMCR0 0x3a8 /* .6. User Monitor Mode Control Register 0 */
486#define SPR_USIA 0x3ab /* .6. User Sampled Instruction Address */
487#define SPR_UMMCR1 0x3ac /* .6. User Monitor Mode Control Register 1 */
488#define SPR_MMCR2_74XX 0x3b0 /* .6. Monitor Mode Control Register 2 */
489#define SPR_MMCR2_74XX_THRESHMULT_32 0x80000000 /* Multiply MMCR0 threshold by 32 */
490#define SPR_MMCR2_74XX_THRESHMULT_2 0x00000000 /* Multiply MMCR0 threshold by 2 */
491#define SPR_PMC5_74XX 0x3b1 /* .6. Performance Counter Register 5 */
492#define SPR_PMC6_74XX 0x3b2 /* .6. Performance Counter Register 6 */
493#define SPR_MMCR0_74XX 0x3b8 /* .6. Monitor Mode Control Register 0 */
494#define SPR_PMC1_74XX 0x3b9 /* .6. Performance Counter Register 1 */
495#define SPR_PMC2_74XX 0x3ba /* .6. Performance Counter Register 2 */
496#define SPR_SIA 0x3bb /* .6. Sampled Instruction Address */
497#define SPR_MMCR1_74XX 0x3bc /* .6. Monitor Mode Control Register 2 */
498
499#define SPR_PMC3_74XX 0x3bd /* .6. Performance Counter Register 3 */
500#define SPR_PMC4_74XX 0x3be /* .6. Performance Counter Register 4 */
501#define SPR_DMISS 0x3d0 /* .68 Data TLB Miss Address Register */
502#define SPR_DCMP 0x3d1 /* .68 Data TLB Compare Register */
503#define SPR_HASH1 0x3d2 /* .68 Primary Hash Address Register */
504#define SPR_HASH2 0x3d3 /* .68 Secondary Hash Address Register */
505#define SPR_IMISS 0x3d4 /* .68 Instruction TLB Miss Address Register */
506#define SPR_TLBMISS 0x3d4 /* .6. TLB Miss Address Register */
507#define SPR_DEAR 0x03d /* ..8 Data Exception Address Register */
508#define SPR_ICMP 0x3d5 /* .68 Instruction TLB Compare Register */
509#define SPR_PTEHI 0x3d5 /* .6. Instruction TLB Compare Register */
510#define SPR_RPA 0x3d6 /* .68 Required Physical Address Register */
511#define SPR_PTELO 0x3d6 /* .6. Required Physical Address Register */
512
513#define SPR_TSR 0x150 /* ..8 Timer Status Register */
514#define SPR_TCR 0x154 /* ..8 Timer Control Register */
515
516#define TSR_ENW 0x80000000 /* Enable Next Watchdog */
517#define TSR_WIS 0x40000000 /* Watchdog Interrupt Status */
518#define TSR_WRS_MASK 0x30000000 /* Watchdog Reset Status */
519#define TSR_WRS_NONE 0x00000000 /* No watchdog reset has occurred */
520#define TSR_WRS_CORE 0x10000000 /* Core reset was forced by the watchdog */
521#define TSR_WRS_CHIP 0x20000000 /* Chip reset was forced by the watchdog */
522#define TSR_WRS_SYSTEM 0x30000000 /* System reset was forced by the watchdog */
523#define TSR_PIS 0x08000000 /* PIT Interrupt Status */
524#define TSR_DIS 0x08000000 /* Decrementer Interrupt Status */
525#define TSR_FIS 0x04000000 /* FIT Interrupt Status */
526
527#define TCR_WP_MASK 0xc0000000 /* Watchdog Period mask */
528#define TCR_WP_2_17 0x00000000 /* 2**17 clocks */
529#define TCR_WP_2_21 0x40000000 /* 2**21 clocks */
530#define TCR_WP_2_25 0x80000000 /* 2**25 clocks */
531#define TCR_WP_2_29 0xc0000000 /* 2**29 clocks */
532#define TCR_WRC_MASK 0x30000000 /* Watchdog Reset Control mask */
533#define TCR_WRC_NONE 0x00000000 /* No watchdog reset */
534#define TCR_WRC_CORE 0x10000000 /* Core reset */
535#define TCR_WRC_CHIP 0x20000000 /* Chip reset */
536#define TCR_WRC_SYSTEM 0x30000000 /* System reset */
537#define TCR_WIE 0x08000000 /* Watchdog Interrupt Enable */
538#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */
539#define TCR_DIE 0x04000000 /* Pecrementer Interrupt Enable */
540#define TCR_FP_MASK 0x03000000 /* FIT Period */
541#define TCR_FP_2_9 0x00000000 /* 2**9 clocks */
542#define TCR_FP_2_13 0x01000000 /* 2**13 clocks */
543#define TCR_FP_2_17 0x02000000 /* 2**17 clocks */
544#define TCR_FP_2_21 0x03000000 /* 2**21 clocks */
545#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */
546#define TCR_ARE 0x00400000 /* Auto Reload Enable */
547
548#define SPR_HID0 0x3f0 /* ..8 Hardware Implementation Register 0 */
549#define SPR_HID1 0x3f1 /* ..8 Hardware Implementation Register 1 */
550#define SPR_HID2 0x3f3 /* ..8 Hardware Implementation Register 2 */
551#define SPR_HID4 0x3f4 /* ..8 Hardware Implementation Register 4 */
552#define SPR_HID5 0x3f6 /* ..8 Hardware Implementation Register 5 */
553#define SPR_HID6 0x3f9 /* ..8 Hardware Implementation Register 6 */
554
555#define SPR_CELL_TSRL 0x380 /* ... Cell BE Thread Status Register */
556#define SPR_CELL_TSCR 0x399 /* ... Cell BE Thread Switch Register */
557
558#if defined(AIM)
559#define SPR_PIR 0x3ff /* .6. Processor Identification Register */
560#elif defined(BOOKE)
561#define SPR_PIR 0x11e /* ..8 Processor Identification Register */
562#endif
563
564#define DBCR0_EDM 0x80000000 /* External Debug Mode */
565#define DBCR0_IDM 0x40000000 /* Internal Debug Mode */
566#define DBCR0_RST_MASK 0x30000000 /* ReSeT */
567#define DBCR0_RST_NONE 0x00000000 /* No action */
568#define DBCR0_RST_CORE 0x10000000 /* Core reset */
569#define DBCR0_RST_CHIP 0x20000000 /* Chip reset */
570#define DBCR0_RST_SYSTEM 0x30000000 /* System reset */
571#define DBCR0_IC 0x08000000 /* Instruction Completion debug event */
572#define DBCR0_BT 0x04000000 /* Branch Taken debug event */
573#define DBCR0_EDE 0x02000000 /* Exception Debug Event */
574#define DBCR0_TDE 0x01000000 /* Trap Debug Event */
575#define DBCR0_IA1 0x00800000 /* IAC (Instruction Address Compare) 1 debug event */
576#define DBCR0_IA2 0x00400000 /* IAC 2 debug event */
577#define DBCR0_IA12 0x00200000 /* Instruction Address Range Compare 1-2 */
578#define DBCR0_IA12X 0x00100000 /* IA12 eXclusive */
579#define DBCR0_IA3 0x00080000 /* IAC 3 debug event */
580#define DBCR0_IA4 0x00040000 /* IAC 4 debug event */
581#define DBCR0_IA34 0x00020000 /* Instruction Address Range Compare 3-4 */
582#define DBCR0_IA34X 0x00010000 /* IA34 eXclusive */
583#define DBCR0_IA12T 0x00008000 /* Instruction Address Range Compare 1-2 range Toggle */
584#define DBCR0_IA34T 0x00004000 /* Instruction Address Range Compare 3-4 range Toggle */
585#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */
586
587#define SPR_IABR 0x3f2 /* ..8 Instruction Address Breakpoint Register 0 */
588#define SPR_DABR 0x3f5 /* .6. Data Address Breakpoint Register */
589#define SPR_MSSCR0 0x3f6 /* .6. Memory SubSystem Control Register */
590#define MSSCR0_SHDEN 0x80000000 /* 0: Shared-state enable */
591#define MSSCR0_SHDPEN3 0x40000000 /* 1: ~SHD[01] signal enable in MEI mode */
592#define MSSCR0_L1INTVEN 0x38000000 /* 2-4: L1 data cache ~HIT intervention enable */
593#define MSSCR0_L2INTVEN 0x07000000 /* 5-7: L2 data cache ~HIT intervention enable*/
594#define MSSCR0_DL1HWF 0x00800000 /* 8: L1 data cache hardware flush */
595#define MSSCR0_MBO 0x00400000 /* 9: must be one */
596#define MSSCR0_EMODE 0x00200000 /* 10: MPX bus mode (read-only) */
597#define MSSCR0_ABD 0x00100000 /* 11: address bus driven (read-only) */
598#define MSSCR0_MBZ 0x000fffff /* 12-31: must be zero */
599#define MSSCR0_L2PFE 0x00000003 /* 30-31: L2 prefetch enable */
600#define SPR_MSSSR0 0x3f7 /* .6. Memory Subsystem Status Register (MPC745x) */
601#define MSSSR0_L2TAG 0x00040000 /* 13: L2 tag parity error */
602#define MSSSR0_L2DAT 0x00020000 /* 14: L2 data parity error */
603#define MSSSR0_L3TAG 0x00010000 /* 15: L3 tag parity error */
604#define MSSSR0_L3DAT 0x00008000 /* 16: L3 data parity error */
605#define MSSSR0_APE 0x00004000 /* 17: Address parity error */
606#define MSSSR0_DPE 0x00002000 /* 18: Data parity error */
607#define MSSSR0_TEA 0x00001000 /* 19: Bus transfer error acknowledge */
608#define SPR_LDSTCR 0x3f8 /* .6. Load/Store Control Register */
609#define SPR_L2PM 0x3f8 /* .6. L2 Private Memory Control Register */
610#define SPR_L2CR 0x3f9 /* .6. L2 Control Register */
611#define L2CR_L2E 0x80000000 /* 0: L2 enable */
612#define L2CR_L2PE 0x40000000 /* 1: L2 data parity enable */
613#define L2CR_L2SIZ 0x30000000 /* 2-3: L2 size */
614#define L2SIZ_2M 0x00000000
615#define L2SIZ_256K 0x10000000
616#define L2SIZ_512K 0x20000000
617#define L2SIZ_1M 0x30000000
618#define L2CR_L2CLK 0x0e000000 /* 4-6: L2 clock ratio */
619#define L2CLK_DIS 0x00000000 /* disable L2 clock */
620#define L2CLK_10 0x02000000 /* core clock / 1 */
621#define L2CLK_15 0x04000000 /* / 1.5 */
622#define L2CLK_20 0x08000000 /* / 2 */
623#define L2CLK_25 0x0a000000 /* / 2.5 */
624#define L2CLK_30 0x0c000000 /* / 3 */
625#define L2CR_L2RAM 0x01800000 /* 7-8: L2 RAM type */
626#define L2RAM_FLOWTHRU_BURST 0x00000000
627#define L2RAM_PIPELINE_BURST 0x01000000
628#define L2RAM_PIPELINE_LATE 0x01800000
629#define L2CR_L2DO 0x00400000 /* 9: L2 data-only.
630 Setting this bit disables instruction
631 caching. */
632#define L2CR_L2I 0x00200000 /* 10: L2 global invalidate. */
633#define L2CR_L2IO_7450 0x00010000 /* 11: L2 instruction-only (MPC745x). */
634#define L2CR_L2CTL 0x00100000 /* 11: L2 RAM control (ZZ enable).
635 Enables automatic operation of the
636 L2ZZ (low-power mode) signal. */
637#define L2CR_L2WT 0x00080000 /* 12: L2 write-through. */
638#define L2CR_L2TS 0x00040000 /* 13: L2 test support. */
639#define L2CR_L2OH 0x00030000 /* 14-15: L2 output hold. */
640#define L2CR_L2DO_7450 0x00010000 /* 15: L2 data-only (MPC745x). */
641#define L2CR_L2SL 0x00008000 /* 16: L2 DLL slow. */
642#define L2CR_L2DF 0x00004000 /* 17: L2 differential clock. */
643#define L2CR_L2BYP 0x00002000 /* 18: L2 DLL bypass. */
644#define L2CR_L2FA 0x00001000 /* 19: L2 flush assist (for software flush). */
645#define L2CR_L2HWF 0x00000800 /* 20: L2 hardware flush. */
646#define L2CR_L2IO 0x00000400 /* 21: L2 instruction-only. */
647#define L2CR_L2CLKSTP 0x00000200 /* 22: L2 clock stop. */
648#define L2CR_L2DRO 0x00000100 /* 23: L2DLL rollover checkstop enable. */
649#define L2CR_L2IP 0x00000001 /* 31: L2 global invalidate in */
650 /* progress (read only). */
651#define SPR_L3CR 0x3fa /* .6. L3 Control Register */
652#define L3CR_L3E 0x80000000 /* 0: L3 enable */
653#define L3CR_L3PE 0x40000000 /* 1: L3 data parity enable */
654#define L3CR_L3APE 0x20000000
655#define L3CR_L3SIZ 0x10000000 /* 3: L3 size (0=1MB, 1=2MB) */
656#define L3CR_L3CLKEN 0x08000000 /* 4: Enables L3_CLK[0:1] */
657#define L3CR_L3CLK 0x03800000
658#define L3CR_L3IO 0x00400000
659#define L3CR_L3CLKEXT 0x00200000
660#define L3CR_L3CKSPEXT 0x00100000
661#define L3CR_L3OH1 0x00080000
662#define L3CR_L3SPO 0x00040000
663#define L3CR_L3CKSP 0x00030000
664#define L3CR_L3PSP 0x0000e000
665#define L3CR_L3REP 0x00001000
666#define L3CR_L3HWF 0x00000800
667#define L3CR_L3I 0x00000400 /* 21: L3 global invalidate */
668#define L3CR_L3RT 0x00000300
669#define L3CR_L3NIRCA 0x00000080
670#define L3CR_L3DO 0x00000040
671#define L3CR_PMEN 0x00000004
672#define L3CR_PMSIZ 0x00000003
673
674#define SPR_THRM1 0x3fc /* .6. Thermal Management Register */
675#define SPR_THRM2 0x3fd /* .6. Thermal Management Register */
676#define SPR_THRM_TIN 0x80000000 /* Thermal interrupt bit (RO) */
677#define SPR_THRM_TIV 0x40000000 /* Thermal interrupt valid (RO) */
678#define SPR_THRM_THRESHOLD(x) ((x) << 23) /* Thermal sensor threshold */
679#define SPR_THRM_TID 0x00000004 /* Thermal interrupt direction */
680#define SPR_THRM_TIE 0x00000002 /* Thermal interrupt enable */
681#define SPR_THRM_VALID 0x00000001 /* Valid bit */
682#define SPR_THRM3 0x3fe /* .6. Thermal Management Register */
683#define SPR_THRM_TIMER(x) ((x) << 1) /* Sampling interval timer */
684#define SPR_THRM_ENABLE 0x00000001 /* TAU Enable */
685#define SPR_FPECR 0x3fe /* .6. Floating-Point Exception Cause Register */
686
687/* Time Base Register declarations */
688#define TBR_TBL 0x10c /* 468 Time Base Lower - read */
689#define TBR_TBU 0x10d /* 468 Time Base Upper - read */
690#define TBR_TBWL 0x11c /* 468 Time Base Lower - supervisor, write */
691#define TBR_TBWU 0x11d /* 468 Time Base Upper - supervisor, write */
692
693/* Performance counter declarations */
694#define PMC_OVERFLOW 0x80000000 /* Counter has overflowed */
695
696/* The first five countable [non-]events are common to many PMC's */
697#define PMCN_NONE 0 /* Count nothing */
698#define PMCN_CYCLES 1 /* Processor cycles */
699#define PMCN_ICOMP 2 /* Instructions completed */
700#define PMCN_TBLTRANS 3 /* TBL bit transitions */
701#define PCMN_IDISPATCH 4 /* Instructions dispatched */
702
703/* Similar things for the 970 PMC direct counters */
704#define PMC970N_NONE 0x8 /* Count nothing */
705#define PMC970N_CYCLES 0xf /* Processor cycles */
706#define PMC970N_ICOMP 0x9 /* Instructions completed */
707
708#if defined(BOOKE)
709
710#define SPR_MCARU 0x239 /* ..8 Machine Check Address register upper bits */
711#define SPR_MCSR 0x23c /* ..8 Machine Check Syndrome register */
712#define MCSR_MCP 0x80000000 /* Machine check input signal to core */
713#define MCSR_L2MMU_MHIT 0x08000000 /* L2 MMU simultaneous hit */
714#define MCSR_NMI 0x00100000 /* Non-maskable interrupt */
715#define MCSR_MAV 0x00080000 /* MCAR address valid */
716#define MCSR_MEA 0x00040000 /* MCAR effective address */
717#define MCSR_IF 0x00010000 /* Instruction fetch error report */
718#define MCSR_LD 0x00008000 /* Load instruction error report */
719#define MCSR_ST 0x00004000 /* Store instruction error report */
720#define MCSR_LDG 0x00002000 /* Guarded load instruction error report */
721#define MCSR_TLBSYNC 0x00000002 /* Simultaneous TLBSYNC detected */
722#define SPR_MCAR 0x23d /* ..8 Machine Check Address register */
723
724#define SPR_ESR 0x003e /* ..8 Exception Syndrome Register */
725#define ESR_PIL 0x08000000 /* Program interrupt - illegal */
726#define ESR_PPR 0x04000000 /* Program interrupt - privileged */
727#define ESR_PTR 0x02000000 /* Program interrupt - trap */
728#define ESR_ST 0x00800000 /* Store operation */
729#define ESR_DLK 0x00200000 /* Data storage, D cache locking */
730#define ESR_ILK 0x00100000 /* Data storage, I cache locking */
731#define ESR_BO 0x00020000 /* Data/instruction storage, byte ordering */
732#define ESR_SPE 0x00000080 /* SPE exception bit */
733
734#define SPR_CSRR0 0x03a /* ..8 58 Critical SRR0 */
735#define SPR_CSRR1 0x03b /* ..8 59 Critical SRR1 */
736#define SPR_MCSRR0 0x23a /* ..8 570 Machine check SRR0 */
737#define SPR_MCSRR1 0x23b /* ..8 571 Machine check SRR1 */
738#define SPR_DSRR0 0x23e /* ..8 574 Debug SRR0<E.ED> */
739#define SPR_DSRR1 0x23f /* ..8 575 Debug SRR1<E.ED> */
740
741#define SPR_MMUCSR0 0x3f4 /* ..8 1012 MMU Control and Status Register 0 */
742#define MMUCSR0_L2TLB0_FI 0x04 /* TLB0 flash invalidate */
743#define MMUCSR0_L2TLB1_FI 0x02 /* TLB1 flash invalidate */
744
745#define SPR_SVR 0x3ff /* ..8 1023 System Version Register */
746#define SVR_MPC8533 0x8034
747#define SVR_MPC8533E 0x803c
748#define SVR_MPC8541 0x8072
749#define SVR_MPC8541E 0x807a
750#define SVR_MPC8548 0x8031
751#define SVR_MPC8548E 0x8039
752#define SVR_MPC8555 0x8071
753#define SVR_MPC8555E 0x8079
754#define SVR_MPC8572 0x80e0
755#define SVR_MPC8572E 0x80e8
756#define SVR_P1011 0x80e5
757#define SVR_P1011E 0x80ed
758#define SVR_P1013 0x80e7
759#define SVR_P1013E 0x80ef
760#define SVR_P1020 0x80e4
761#define SVR_P1020E 0x80ec
762#define SVR_P1022 0x80e6
763#define SVR_P1022E 0x80ee
764#define SVR_P2010 0x80e3
765#define SVR_P2010E 0x80eb
766#define SVR_P2020 0x80e2
767#define SVR_P2020E 0x80ea
768#define SVR_P2041 0x8210
769#define SVR_P2041E 0x8218
770#define SVR_P3041 0x8211
771#define SVR_P3041E 0x8219
772#define SVR_P4040 0x8200
773#define SVR_P4040E 0x8208
774#define SVR_P4080 0x8201
775#define SVR_P4080E 0x8209
776#define SVR_P5010 0x8221
777#define SVR_P5010E 0x8229
778#define SVR_P5020 0x8220
779#define SVR_P5020E 0x8228
780#define SVR_P5021 0x8205
781#define SVR_P5021E 0x820d
782#define SVR_P5040 0x8204
783#define SVR_P5040E 0x820c
784#define SVR_VER(svr) (((svr) >> 16) & 0xffff)
785
786#define SPR_PID0 0x030 /* ..8 Process ID Register 0 */
787#define SPR_PID1 0x279 /* ..8 Process ID Register 1 */
788#define SPR_PID2 0x27a /* ..8 Process ID Register 2 */
789
790#define SPR_TLB0CFG 0x2B0 /* ..8 TLB 0 Config Register */
791#define SPR_TLB1CFG 0x2B1 /* ..8 TLB 1 Config Register */
792#define TLBCFG_ASSOC_MASK 0xff000000 /* Associativity of TLB */
793#define TLBCFG_ASSOC_SHIFT 24
794#define TLBCFG_NENTRY_MASK 0x00000fff /* Number of entries in TLB */
795
796#define SPR_IVPR 0x03f /* ..8 Interrupt Vector Prefix Register */
797#define SPR_IVOR0 0x190 /* ..8 Critical input */
798#define SPR_IVOR1 0x191 /* ..8 Machine check */
799#define SPR_IVOR2 0x192
800#define SPR_IVOR3 0x193
801#define SPR_IVOR4 0x194
802#define SPR_IVOR5 0x195
803#define SPR_IVOR6 0x196
804#define SPR_IVOR7 0x197
805#define SPR_IVOR8 0x198
806#define SPR_IVOR9 0x199
807#define SPR_IVOR10 0x19a
808#define SPR_IVOR11 0x19b
809#define SPR_IVOR12 0x19c
810#define SPR_IVOR13 0x19d
811#define SPR_IVOR14 0x19e
812#define SPR_IVOR15 0x19f
813#define SPR_IVOR32 0x210
814#define SPR_IVOR33 0x211
815#define SPR_IVOR34 0x212
816#define SPR_IVOR35 0x213
817
818#define SPR_MAS0 0x270 /* ..8 MMU Assist Register 0 Book-E/e500 */
819#define SPR_MAS1 0x271 /* ..8 MMU Assist Register 1 Book-E/e500 */
820#define SPR_MAS2 0x272 /* ..8 MMU Assist Register 2 Book-E/e500 */
821#define SPR_MAS3 0x273 /* ..8 MMU Assist Register 3 Book-E/e500 */
822#define SPR_MAS4 0x274 /* ..8 MMU Assist Register 4 Book-E/e500 */
823#define SPR_MAS5 0x275 /* ..8 MMU Assist Register 5 Book-E */
824#define SPR_MAS6 0x276 /* ..8 MMU Assist Register 6 Book-E/e500 */
825#define SPR_MAS7 0x3B0 /* ..8 MMU Assist Register 7 Book-E/e500 */
826#define SPR_MAS8 0x155 /* ..8 MMU Assist Register 8 Book-E/e500 */
827
828#define SPR_L1CFG0 0x203 /* ..8 L1 cache configuration register 0 */
829#define SPR_L1CFG1 0x204 /* ..8 L1 cache configuration register 1 */
830
831#define SPR_CCR1 0x378
832#define CCR1_L2COBE 0x00000040
833
834#define DCR_L2DCDCRAI 0x0000 /* L2 D-Cache DCR Address Pointer */
835#define DCR_L2DCDCRDI 0x0001 /* L2 D-Cache DCR Data Indirect */
836#define DCR_L2CR0 0x00 /* L2 Cache Configuration Register 0 */
837#define L2CR0_AS 0x30000000
838
839#define SPR_L1CSR0 0x3F2 /* ..8 L1 Cache Control and Status Register 0 */
840#define L1CSR0_DCPE 0x00010000 /* Data Cache Parity Enable */
841#define L1CSR0_DCLFR 0x00000100 /* Data Cache Lock Bits Flash Reset */
842#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
843#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
844#define SPR_L1CSR1 0x3F3 /* ..8 L1 Cache Control and Status Register 1 */
845#define L1CSR1_ICPE 0x00010000 /* Instruction Cache Parity Enable */
846#define L1CSR1_ICUL 0x00000400 /* Instr Cache Unable to Lock */
847#define L1CSR1_ICLFR 0x00000100 /* Instruction Cache Lock Bits Flash Reset */
848#define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
849#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
850
851#define SPR_L2CFG0 0x207 /* ..8 L2 Configuration Register 0 */
852#define SPR_L2CSR0 0x3F9 /* ..8 L2 Cache Control and Status Register 0 */
853#define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */
854#define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity Enable */
855#define L2CSR0_L2FI 0x00200000 /* L2 Cache Flash Invalidate */
856#define L2CSR0_L2LFC 0x00000400 /* L2 Cache Lock Flags Clear */
857
858#define SPR_BUCSR 0x3F5 /* ..8 Branch Unit Control and Status Register */
859#define BUCSR_BPEN 0x00000001 /* Branch Prediction Enable */
860#define BUCSR_BBFI 0x00000200 /* Branch Buffer Flash Invalidate */
861
862#endif /* BOOKE */
863#endif /* !_POWERPC_SPR_H_ */