master
1/*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (C) 2012-2013 Intel Corporation
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#ifndef __NVME_H__
30#define __NVME_H__
31
32#ifdef _KERNEL
33#include <sys/types.h>
34#endif
35
36#include <sys/param.h>
37#include <sys/endian.h>
38
39#define NVME_PASSTHROUGH_CMD _IOWR('n', 0, struct nvme_pt_command)
40#define NVME_RESET_CONTROLLER _IO('n', 1)
41#define NVME_GET_NSID _IOR('n', 2, struct nvme_get_nsid)
42#define NVME_GET_MAX_XFER_SIZE _IOR('n', 3, uint64_t)
43
44#define NVME_IO_TEST _IOWR('n', 100, struct nvme_io_test)
45#define NVME_BIO_TEST _IOWR('n', 101, struct nvme_io_test)
46
47/*
48 * Macros to deal with NVME revisions, as defined VS register
49 */
50#define NVME_REV(x, y) (((x) << 16) | ((y) << 8))
51#define NVME_MAJOR(r) (((r) >> 16) & 0xffff)
52#define NVME_MINOR(r) (((r) >> 8) & 0xff)
53
54/*
55 * Use to mark a command to apply to all namespaces, or to retrieve global
56 * log pages.
57 */
58#define NVME_GLOBAL_NAMESPACE_TAG ((uint32_t)0xFFFFFFFF)
59
60/* Host memory buffer sizes are always in 4096 byte chunks */
61#define NVME_HMB_UNITS 4096
62
63/* Many items are expressed in terms of power of two times MPS */
64#define NVME_MPS_SHIFT 12
65
66/* Limits on queue sizes: See 4.1.3 Queue Size in NVMe 1.4b. */
67#define NVME_MIN_ADMIN_ENTRIES 2
68#define NVME_MAX_ADMIN_ENTRIES 4096
69
70#define NVME_MIN_IO_ENTRIES 2
71#define NVME_MAX_IO_ENTRIES 65536
72
73/* Register field definitions */
74#define NVME_CAP_LO_REG_MQES_SHIFT (0)
75#define NVME_CAP_LO_REG_MQES_MASK (0xFFFF)
76#define NVME_CAP_LO_REG_CQR_SHIFT (16)
77#define NVME_CAP_LO_REG_CQR_MASK (0x1)
78#define NVME_CAP_LO_REG_AMS_SHIFT (17)
79#define NVME_CAP_LO_REG_AMS_MASK (0x3)
80#define NVME_CAP_LO_REG_TO_SHIFT (24)
81#define NVME_CAP_LO_REG_TO_MASK (0xFF)
82#define NVME_CAP_LO_MQES(x) \
83 NVMEV(NVME_CAP_LO_REG_MQES, x)
84#define NVME_CAP_LO_CQR(x) \
85 NVMEV(NVME_CAP_LO_REG_CQR, x)
86#define NVME_CAP_LO_AMS(x) \
87 NVMEV(NVME_CAP_LO_REG_AMS, x)
88#define NVME_CAP_LO_TO(x) \
89 NVMEV(NVME_CAP_LO_REG_TO, x)
90
91#define NVME_CAP_HI_REG_DSTRD_SHIFT (0)
92#define NVME_CAP_HI_REG_DSTRD_MASK (0xF)
93#define NVME_CAP_HI_REG_NSSRS_SHIFT (4)
94#define NVME_CAP_HI_REG_NSSRS_MASK (0x1)
95#define NVME_CAP_HI_REG_CSS_SHIFT (5)
96#define NVME_CAP_HI_REG_CSS_MASK (0xff)
97#define NVME_CAP_HI_REG_CSS_NVM_SHIFT (5)
98#define NVME_CAP_HI_REG_CSS_NVM_MASK (0x1)
99#define NVME_CAP_HI_REG_BPS_SHIFT (13)
100#define NVME_CAP_HI_REG_BPS_MASK (0x1)
101#define NVME_CAP_HI_REG_CPS_SHIFT (14)
102#define NVME_CAP_HI_REG_CPS_MASK (0x3)
103#define NVME_CAP_HI_REG_MPSMIN_SHIFT (16)
104#define NVME_CAP_HI_REG_MPSMIN_MASK (0xF)
105#define NVME_CAP_HI_REG_MPSMAX_SHIFT (20)
106#define NVME_CAP_HI_REG_MPSMAX_MASK (0xF)
107#define NVME_CAP_HI_REG_PMRS_SHIFT (24)
108#define NVME_CAP_HI_REG_PMRS_MASK (0x1)
109#define NVME_CAP_HI_REG_CMBS_SHIFT (25)
110#define NVME_CAP_HI_REG_CMBS_MASK (0x1)
111#define NVME_CAP_HI_REG_NSSS_SHIFT (26)
112#define NVME_CAP_HI_REG_NSSS_MASK (0x1)
113#define NVME_CAP_HI_REG_CRWMS_SHIFT (27)
114#define NVME_CAP_HI_REG_CRWMS_MASK (0x1)
115#define NVME_CAP_HI_REG_CRIMS_SHIFT (28)
116#define NVME_CAP_HI_REG_CRIMS_MASK (0x1)
117#define NVME_CAP_HI_DSTRD(x) \
118 NVMEV(NVME_CAP_HI_REG_DSTRD, x)
119#define NVME_CAP_HI_NSSRS(x) \
120 NVMEV(NVME_CAP_HI_REG_NSSRS, x)
121#define NVME_CAP_HI_CSS(x) \
122 NVMEV(NVME_CAP_HI_REG_CSS, x)
123#define NVME_CAP_HI_CSS_NVM(x) \
124 NVMEV(NVME_CAP_HI_REG_CSS_NVM, x)
125#define NVME_CAP_HI_BPS(x) \
126 NVMEV(NVME_CAP_HI_REG_BPS, x)
127#define NVME_CAP_HI_CPS(x) \
128 NVMEV(NVME_CAP_HI_REG_CPS, x)
129#define NVME_CAP_HI_MPSMIN(x) \
130 NVMEV(NVME_CAP_HI_REG_MPSMIN, x)
131#define NVME_CAP_HI_MPSMAX(x) \
132 NVMEV(NVME_CAP_HI_REG_MPSMAX, x)
133#define NVME_CAP_HI_PMRS(x) \
134 NVMEV(NVME_CAP_HI_REG_PMRS, x)
135#define NVME_CAP_HI_CMBS(x) \
136 NVMEV(NVME_CAP_HI_REG_CMBS, x)
137#define NVME_CAP_HI_NSSS(x) \
138 NVMEV(NVME_CAP_HI_REG_NSSS, x)
139#define NVME_CAP_HI_CRWMS(x) \
140 NVMEV(NVME_CAP_HI_REG_CRWMS, x)
141#define NVME_CAP_HI_CRIMS(x) \
142 NVMEV(NVME_CAP_HI_REG_CRIMS, x)
143
144#define NVME_CC_REG_EN_SHIFT (0)
145#define NVME_CC_REG_EN_MASK (0x1)
146#define NVME_CC_REG_CSS_SHIFT (4)
147#define NVME_CC_REG_CSS_MASK (0x7)
148#define NVME_CC_REG_MPS_SHIFT (7)
149#define NVME_CC_REG_MPS_MASK (0xF)
150#define NVME_CC_REG_AMS_SHIFT (11)
151#define NVME_CC_REG_AMS_MASK (0x7)
152#define NVME_CC_REG_SHN_SHIFT (14)
153#define NVME_CC_REG_SHN_MASK (0x3)
154#define NVME_CC_REG_IOSQES_SHIFT (16)
155#define NVME_CC_REG_IOSQES_MASK (0xF)
156#define NVME_CC_REG_IOCQES_SHIFT (20)
157#define NVME_CC_REG_IOCQES_MASK (0xF)
158#define NVME_CC_REG_CRIME_SHIFT (24)
159#define NVME_CC_REG_CRIME_MASK (0x1)
160
161#define NVME_CSTS_REG_RDY_SHIFT (0)
162#define NVME_CSTS_REG_RDY_MASK (0x1)
163#define NVME_CSTS_REG_CFS_SHIFT (1)
164#define NVME_CSTS_REG_CFS_MASK (0x1)
165#define NVME_CSTS_REG_SHST_SHIFT (2)
166#define NVME_CSTS_REG_SHST_MASK (0x3)
167#define NVME_CSTS_REG_NVSRO_SHIFT (4)
168#define NVME_CSTS_REG_NVSRO_MASK (0x1)
169#define NVME_CSTS_REG_PP_SHIFT (5)
170#define NVME_CSTS_REG_PP_MASK (0x1)
171#define NVME_CSTS_REG_ST_SHIFT (6)
172#define NVME_CSTS_REG_ST_MASK (0x1)
173
174#define NVME_CSTS_GET_SHST(csts) \
175 NVMEV(NVME_CSTS_REG_SHST, csts)
176
177#define NVME_AQA_REG_ASQS_SHIFT (0)
178#define NVME_AQA_REG_ASQS_MASK (0xFFF)
179#define NVME_AQA_REG_ACQS_SHIFT (16)
180#define NVME_AQA_REG_ACQS_MASK (0xFFF)
181
182#define NVME_PMRCAP_REG_RDS_SHIFT (3)
183#define NVME_PMRCAP_REG_RDS_MASK (0x1)
184#define NVME_PMRCAP_REG_WDS_SHIFT (4)
185#define NVME_PMRCAP_REG_WDS_MASK (0x1)
186#define NVME_PMRCAP_REG_BIR_SHIFT (5)
187#define NVME_PMRCAP_REG_BIR_MASK (0x7)
188#define NVME_PMRCAP_REG_PMRTU_SHIFT (8)
189#define NVME_PMRCAP_REG_PMRTU_MASK (0x3)
190#define NVME_PMRCAP_REG_PMRWBM_SHIFT (10)
191#define NVME_PMRCAP_REG_PMRWBM_MASK (0xf)
192#define NVME_PMRCAP_REG_PMRTO_SHIFT (16)
193#define NVME_PMRCAP_REG_PMRTO_MASK (0xff)
194#define NVME_PMRCAP_REG_CMSS_SHIFT (24)
195#define NVME_PMRCAP_REG_CMSS_MASK (0x1)
196
197#define NVME_PMRCAP_RDS(x) \
198 NVMEV(NVME_PMRCAP_REG_RDS, x)
199#define NVME_PMRCAP_WDS(x) \
200 NVMEV(NVME_PMRCAP_REG_WDS, x)
201#define NVME_PMRCAP_BIR(x) \
202 NVMEV(NVME_PMRCAP_REG_BIR, x)
203#define NVME_PMRCAP_PMRTU(x) \
204 NVMEV(NVME_PMRCAP_REG_PMRTU, x)
205#define NVME_PMRCAP_PMRWBM(x) \
206 NVMEV(NVME_PMRCAP_REG_PMRWBM, x)
207#define NVME_PMRCAP_PMRTO(x) \
208 NVMEV(NVME_PMRCAP_REG_PMRTO, x)
209#define NVME_PMRCAP_CMSS(x) \
210 NVMEV(NVME_PMRCAP_REG_CMSS, x)
211
212/* Command field definitions */
213
214#define NVME_CMD_FUSE_SHIFT (0)
215#define NVME_CMD_FUSE_MASK (0x3)
216
217enum nvme_psdt {
218 NVME_PSDT_PRP = 0x0,
219 NVME_PSDT_SGL = 0x1,
220 NVME_PSDT_SGL_MPTR = 0x2
221};
222#define NVME_CMD_PSDT_SHIFT (6)
223#define NVME_CMD_PSDT_MASK (0x3)
224
225
226#define NVME_STATUS_P_SHIFT (0)
227#define NVME_STATUS_P_MASK (0x1)
228#define NVME_STATUS_SC_SHIFT (1)
229#define NVME_STATUS_SC_MASK (0xFF)
230#define NVME_STATUS_SCT_SHIFT (9)
231#define NVME_STATUS_SCT_MASK (0x7)
232#define NVME_STATUS_CRD_SHIFT (12)
233#define NVME_STATUS_CRD_MASK (0x3)
234#define NVME_STATUS_M_SHIFT (14)
235#define NVME_STATUS_M_MASK (0x1)
236#define NVME_STATUS_DNR_SHIFT (15)
237#define NVME_STATUS_DNR_MASK (0x1)
238
239#define NVME_STATUS_GET_P(st) \
240 NVMEV(NVME_STATUS_P, st)
241#define NVME_STATUS_GET_SC(st) \
242 NVMEV(NVME_STATUS_SC, st)
243#define NVME_STATUS_GET_SCT(st) \
244 NVMEV(NVME_STATUS_SCT, st)
245#define NVME_STATUS_GET_CRD(st) \
246 NVMEV(NVME_STATUS_CRD, st)
247#define NVME_STATUS_GET_M(st) \
248 NVMEV(NVME_STATUS_M, st)
249#define NVME_STATUS_GET_DNR(st) \
250 NVMEV(NVME_STATUS_DNR, st)
251
252#define NVME_PWR_ST_MPS_SHIFT (0)
253#define NVME_PWR_ST_MPS_MASK (0x1)
254#define NVME_PWR_ST_NOPS_SHIFT (1)
255#define NVME_PWR_ST_NOPS_MASK (0x1)
256#define NVME_PWR_ST_RRT_SHIFT (0)
257#define NVME_PWR_ST_RRT_MASK (0x1F)
258#define NVME_PWR_ST_RRL_SHIFT (0)
259#define NVME_PWR_ST_RRL_MASK (0x1F)
260#define NVME_PWR_ST_RWT_SHIFT (0)
261#define NVME_PWR_ST_RWT_MASK (0x1F)
262#define NVME_PWR_ST_RWL_SHIFT (0)
263#define NVME_PWR_ST_RWL_MASK (0x1F)
264#define NVME_PWR_ST_IPS_SHIFT (6)
265#define NVME_PWR_ST_IPS_MASK (0x3)
266#define NVME_PWR_ST_APW_SHIFT (0)
267#define NVME_PWR_ST_APW_MASK (0x7)
268#define NVME_PWR_ST_APS_SHIFT (6)
269#define NVME_PWR_ST_APS_MASK (0x3)
270
271/** Controller Multi-path I/O and Namespace Sharing Capabilities */
272/* More then one port */
273#define NVME_CTRLR_DATA_MIC_MPORTS_SHIFT (0)
274#define NVME_CTRLR_DATA_MIC_MPORTS_MASK (0x1)
275/* More then one controller */
276#define NVME_CTRLR_DATA_MIC_MCTRLRS_SHIFT (1)
277#define NVME_CTRLR_DATA_MIC_MCTRLRS_MASK (0x1)
278/* SR-IOV Virtual Function */
279#define NVME_CTRLR_DATA_MIC_SRIOVVF_SHIFT (2)
280#define NVME_CTRLR_DATA_MIC_SRIOVVF_MASK (0x1)
281/* Asymmetric Namespace Access Reporting */
282#define NVME_CTRLR_DATA_MIC_ANAR_SHIFT (3)
283#define NVME_CTRLR_DATA_MIC_ANAR_MASK (0x1)
284
285/** OAES - Optional Asynchronous Events Supported */
286/* supports Namespace Attribute Notices event */
287#define NVME_CTRLR_DATA_OAES_NS_ATTR_SHIFT (8)
288#define NVME_CTRLR_DATA_OAES_NS_ATTR_MASK (0x1)
289/* supports Firmware Activation Notices event */
290#define NVME_CTRLR_DATA_OAES_FW_ACTIVATE_SHIFT (9)
291#define NVME_CTRLR_DATA_OAES_FW_ACTIVATE_MASK (0x1)
292/* supports Asymmetric Namespace Access Change Notices event */
293#define NVME_CTRLR_DATA_OAES_ASYM_NS_CHANGE_SHIFT (11)
294#define NVME_CTRLR_DATA_OAES_ASYM_NS_CHANGE_MASK (0x1)
295/* supports Predictable Latency Event Aggregate Log Change Notices event */
296#define NVME_CTRLR_DATA_OAES_PREDICT_LATENCY_SHIFT (12)
297#define NVME_CTRLR_DATA_OAES_PREDICT_LATENCY_MASK (0x1)
298/* supports LBA Status Information Notices event */
299#define NVME_CTRLR_DATA_OAES_LBA_STATUS_SHIFT (13)
300#define NVME_CTRLR_DATA_OAES_LBA_STATUS_MASK (0x1)
301/* supports Endurance Group Event Aggregate Log Page Changes Notices event */
302#define NVME_CTRLR_DATA_OAES_ENDURANCE_GROUP_SHIFT (14)
303#define NVME_CTRLR_DATA_OAES_ENDURANCE_GROUP_MASK (0x1)
304/* supports Normal NVM Subsystem Shutdown event */
305#define NVME_CTRLR_DATA_OAES_NORMAL_SHUTDOWN_SHIFT (15)
306#define NVME_CTRLR_DATA_OAES_NORMAL_SHUTDOWN_MASK (0x1)
307/* supports Zone Descriptor Changed Notices event */
308#define NVME_CTRLR_DATA_OAES_ZONE_DESC_CHANGE_SHIFT (27)
309#define NVME_CTRLR_DATA_OAES_ZONE_DESC_CHANGE_MASK (0x1)
310/* supports Discovery Log Page Change Notification event */
311#define NVME_CTRLR_DATA_OAES_LOG_PAGE_CHANGE_SHIFT (31)
312#define NVME_CTRLR_DATA_OAES_LOG_PAGE_CHANGE_MASK (0x1)
313
314/** CTRATT - Controller Attributes */
315/* supports 128-bit Host Identifier */
316#define NVME_CTRLR_DATA_CTRATT_128BIT_HOSTID_SHIFT (0)
317#define NVME_CTRLR_DATA_CTRATT_128BIT_HOSTID_MASK (0x1)
318/* supports Non-Operational Power State Permissive Mode */
319#define NVME_CTRLR_DATA_CTRATT_NONOP_POWER_STATE_SHIFT (1)
320#define NVME_CTRLR_DATA_CTRATT_NONOP_POWER_STATE_MASK (0x1)
321/* supports NVM Sets */
322#define NVME_CTRLR_DATA_CTRATT_NVM_SETS_SHIFT (2)
323#define NVME_CTRLR_DATA_CTRATT_NVM_SETS_MASK (0x1)
324/* supports Read Recovery Levels */
325#define NVME_CTRLR_DATA_CTRATT_READ_RECOVERY_LVLS_SHIFT (3)
326#define NVME_CTRLR_DATA_CTRATT_READ_RECOVERY_LVLS_MASK (0x1)
327/* supports Endurance Groups */
328#define NVME_CTRLR_DATA_CTRATT_ENDURANCE_GROUPS_SHIFT (4)
329#define NVME_CTRLR_DATA_CTRATT_ENDURANCE_GROUPS_MASK (0x1)
330/* supports Predictable Latency Mode */
331#define NVME_CTRLR_DATA_CTRATT_PREDICTABLE_LATENCY_SHIFT (5)
332#define NVME_CTRLR_DATA_CTRATT_PREDICTABLE_LATENCY_MASK (0x1)
333/* supports Traffic Based Keep Alive Support */
334#define NVME_CTRLR_DATA_CTRATT_TBKAS_SHIFT (6)
335#define NVME_CTRLR_DATA_CTRATT_TBKAS_MASK (0x1)
336/* supports Namespace Granularity */
337#define NVME_CTRLR_DATA_CTRATT_NAMESPACE_GRANULARITY_SHIFT (7)
338#define NVME_CTRLR_DATA_CTRATT_NAMESPACE_GRANULARITY_MASK (0x1)
339/* supports SQ Associations */
340#define NVME_CTRLR_DATA_CTRATT_SQ_ASSOCIATIONS_SHIFT (8)
341#define NVME_CTRLR_DATA_CTRATT_SQ_ASSOCIATIONS_MASK (0x1)
342/* supports UUID List */
343#define NVME_CTRLR_DATA_CTRATT_UUID_LIST_SHIFT (9)
344#define NVME_CTRLR_DATA_CTRATT_UUID_LIST_MASK (0x1)
345
346/** OACS - optional admin command support */
347/* supports security send/receive commands */
348#define NVME_CTRLR_DATA_OACS_SECURITY_SHIFT (0)
349#define NVME_CTRLR_DATA_OACS_SECURITY_MASK (0x1)
350/* supports format nvm command */
351#define NVME_CTRLR_DATA_OACS_FORMAT_SHIFT (1)
352#define NVME_CTRLR_DATA_OACS_FORMAT_MASK (0x1)
353/* supports firmware activate/download commands */
354#define NVME_CTRLR_DATA_OACS_FIRMWARE_SHIFT (2)
355#define NVME_CTRLR_DATA_OACS_FIRMWARE_MASK (0x1)
356/* supports namespace management commands */
357#define NVME_CTRLR_DATA_OACS_NSMGMT_SHIFT (3)
358#define NVME_CTRLR_DATA_OACS_NSMGMT_MASK (0x1)
359/* supports Device Self-test command */
360#define NVME_CTRLR_DATA_OACS_SELFTEST_SHIFT (4)
361#define NVME_CTRLR_DATA_OACS_SELFTEST_MASK (0x1)
362/* supports Directives */
363#define NVME_CTRLR_DATA_OACS_DIRECTIVES_SHIFT (5)
364#define NVME_CTRLR_DATA_OACS_DIRECTIVES_MASK (0x1)
365/* supports NVMe-MI Send/Receive */
366#define NVME_CTRLR_DATA_OACS_NVMEMI_SHIFT (6)
367#define NVME_CTRLR_DATA_OACS_NVMEMI_MASK (0x1)
368/* supports Virtualization Management */
369#define NVME_CTRLR_DATA_OACS_VM_SHIFT (7)
370#define NVME_CTRLR_DATA_OACS_VM_MASK (0x1)
371/* supports Doorbell Buffer Config */
372#define NVME_CTRLR_DATA_OACS_DBBUFFER_SHIFT (8)
373#define NVME_CTRLR_DATA_OACS_DBBUFFER_MASK (0x1)
374/* supports Get LBA Status */
375#define NVME_CTRLR_DATA_OACS_GETLBA_SHIFT (9)
376#define NVME_CTRLR_DATA_OACS_GETLBA_MASK (0x1)
377
378/** firmware updates */
379/* first slot is read-only */
380#define NVME_CTRLR_DATA_FRMW_SLOT1_RO_SHIFT (0)
381#define NVME_CTRLR_DATA_FRMW_SLOT1_RO_MASK (0x1)
382/* number of firmware slots */
383#define NVME_CTRLR_DATA_FRMW_NUM_SLOTS_SHIFT (1)
384#define NVME_CTRLR_DATA_FRMW_NUM_SLOTS_MASK (0x7)
385/* firmware activation without reset */
386#define NVME_CTRLR_DATA_FRMW_ACT_WO_RESET_SHIFT (4)
387#define NVME_CTRLR_DATA_FRMW_ACT_WO_RESET_MASK (0x1)
388
389/** log page attributes */
390/* per namespace smart/health log page */
391#define NVME_CTRLR_DATA_LPA_NS_SMART_SHIFT (0)
392#define NVME_CTRLR_DATA_LPA_NS_SMART_MASK (0x1)
393/* extended data for Get Log Page command */
394#define NVME_CTRLR_DATA_LPA_EXT_DATA_SHIFT (2)
395#define NVME_CTRLR_DATA_LPA_EXT_DATA_MASK (0x1)
396
397/** AVSCC - admin vendor specific command configuration */
398/* admin vendor specific commands use spec format */
399#define NVME_CTRLR_DATA_AVSCC_SPEC_FORMAT_SHIFT (0)
400#define NVME_CTRLR_DATA_AVSCC_SPEC_FORMAT_MASK (0x1)
401
402/** Autonomous Power State Transition Attributes */
403/* Autonomous Power State Transitions supported */
404#define NVME_CTRLR_DATA_APSTA_APST_SUPP_SHIFT (0)
405#define NVME_CTRLR_DATA_APSTA_APST_SUPP_MASK (0x1)
406
407/** Sanitize Capabilities */
408/* Crypto Erase Support */
409#define NVME_CTRLR_DATA_SANICAP_CES_SHIFT (0)
410#define NVME_CTRLR_DATA_SANICAP_CES_MASK (0x1)
411/* Block Erase Support */
412#define NVME_CTRLR_DATA_SANICAP_BES_SHIFT (1)
413#define NVME_CTRLR_DATA_SANICAP_BES_MASK (0x1)
414/* Overwrite Support */
415#define NVME_CTRLR_DATA_SANICAP_OWS_SHIFT (2)
416#define NVME_CTRLR_DATA_SANICAP_OWS_MASK (0x1)
417/* No-Deallocate Inhibited */
418#define NVME_CTRLR_DATA_SANICAP_NDI_SHIFT (29)
419#define NVME_CTRLR_DATA_SANICAP_NDI_MASK (0x1)
420/* No-Deallocate Modifies Media After Sanitize */
421#define NVME_CTRLR_DATA_SANICAP_NODMMAS_SHIFT (30)
422#define NVME_CTRLR_DATA_SANICAP_NODMMAS_MASK (0x3)
423#define NVME_CTRLR_DATA_SANICAP_NODMMAS_UNDEF (0)
424#define NVME_CTRLR_DATA_SANICAP_NODMMAS_NO (1)
425#define NVME_CTRLR_DATA_SANICAP_NODMMAS_YES (2)
426
427/** submission queue entry size */
428#define NVME_CTRLR_DATA_SQES_MIN_SHIFT (0)
429#define NVME_CTRLR_DATA_SQES_MIN_MASK (0xF)
430#define NVME_CTRLR_DATA_SQES_MAX_SHIFT (4)
431#define NVME_CTRLR_DATA_SQES_MAX_MASK (0xF)
432
433/** completion queue entry size */
434#define NVME_CTRLR_DATA_CQES_MIN_SHIFT (0)
435#define NVME_CTRLR_DATA_CQES_MIN_MASK (0xF)
436#define NVME_CTRLR_DATA_CQES_MAX_SHIFT (4)
437#define NVME_CTRLR_DATA_CQES_MAX_MASK (0xF)
438
439/** optional nvm command support */
440#define NVME_CTRLR_DATA_ONCS_COMPARE_SHIFT (0)
441#define NVME_CTRLR_DATA_ONCS_COMPARE_MASK (0x1)
442#define NVME_CTRLR_DATA_ONCS_WRITE_UNC_SHIFT (1)
443#define NVME_CTRLR_DATA_ONCS_WRITE_UNC_MASK (0x1)
444#define NVME_CTRLR_DATA_ONCS_DSM_SHIFT (2)
445#define NVME_CTRLR_DATA_ONCS_DSM_MASK (0x1)
446#define NVME_CTRLR_DATA_ONCS_WRZERO_SHIFT (3)
447#define NVME_CTRLR_DATA_ONCS_WRZERO_MASK (0x1)
448#define NVME_CTRLR_DATA_ONCS_SAVEFEAT_SHIFT (4)
449#define NVME_CTRLR_DATA_ONCS_SAVEFEAT_MASK (0x1)
450#define NVME_CTRLR_DATA_ONCS_RESERV_SHIFT (5)
451#define NVME_CTRLR_DATA_ONCS_RESERV_MASK (0x1)
452#define NVME_CTRLR_DATA_ONCS_TIMESTAMP_SHIFT (6)
453#define NVME_CTRLR_DATA_ONCS_TIMESTAMP_MASK (0x1)
454#define NVME_CTRLR_DATA_ONCS_VERIFY_SHIFT (7)
455#define NVME_CTRLR_DATA_ONCS_VERIFY_MASK (0x1)
456
457/** Fused Operation Support */
458#define NVME_CTRLR_DATA_FUSES_CNW_SHIFT (0)
459#define NVME_CTRLR_DATA_FUSES_CNW_MASK (0x1)
460
461/** Format NVM Attributes */
462#define NVME_CTRLR_DATA_FNA_FORMAT_ALL_SHIFT (0)
463#define NVME_CTRLR_DATA_FNA_FORMAT_ALL_MASK (0x1)
464#define NVME_CTRLR_DATA_FNA_ERASE_ALL_SHIFT (1)
465#define NVME_CTRLR_DATA_FNA_ERASE_ALL_MASK (0x1)
466#define NVME_CTRLR_DATA_FNA_CRYPTO_ERASE_SHIFT (2)
467#define NVME_CTRLR_DATA_FNA_CRYPTO_ERASE_MASK (0x1)
468
469/** volatile write cache */
470/* volatile write cache present */
471#define NVME_CTRLR_DATA_VWC_PRESENT_SHIFT (0)
472#define NVME_CTRLR_DATA_VWC_PRESENT_MASK (0x1)
473/* flush all namespaces supported */
474#define NVME_CTRLR_DATA_VWC_ALL_SHIFT (1)
475#define NVME_CTRLR_DATA_VWC_ALL_MASK (0x3)
476#define NVME_CTRLR_DATA_VWC_ALL_UNKNOWN (0)
477#define NVME_CTRLR_DATA_VWC_ALL_NO (2)
478#define NVME_CTRLR_DATA_VWC_ALL_YES (3)
479
480/** SGL Support */
481/* NVM command set SGL support */
482#define NVME_CTRLR_DATA_SGLS_NVM_COMMAND_SET_SHIFT (0)
483#define NVME_CTRLR_DATA_SGLS_NVM_COMMAND_SET_MASK (0x3)
484#define NVME_CTRLR_DATA_SGLS_KEYED_DATA_BLOCK_SHIFT (2)
485#define NVME_CTRLR_DATA_SGLS_KEYED_DATA_BLOCK_MASK (0x1)
486#define NVME_CTRLR_DATA_SGLS_BIT_BUCKET_SHIFT (16)
487#define NVME_CTRLR_DATA_SGLS_BIT_BUCKET_MASK (0x1)
488#define NVME_CTRLR_DATA_SGLS_CONTIG_MPTR_SHIFT (17)
489#define NVME_CTRLR_DATA_SGLS_CONTIG_MPTR_MASK (0x1)
490#define NVME_CTRLR_DATA_SGLS_OVERSIZED_SHIFT (18)
491#define NVME_CTRLR_DATA_SGLS_OVERSIZED_MASK (0x1)
492#define NVME_CTRLR_DATA_SGLS_MPTR_SGL_SHIFT (19)
493#define NVME_CTRLR_DATA_SGLS_MPTR_SGL_MASK (0x1)
494#define NVME_CTRLR_DATA_SGLS_ADDRESS_AS_OFFSET_SHIFT (20)
495#define NVME_CTRLR_DATA_SGLS_ADDRESS_AS_OFFSET_MASK (0x1)
496#define NVME_CTRLR_DATA_SGLS_TRANSPORT_DATA_BLOCK_SHIFT (21)
497#define NVME_CTRLR_DATA_SGLS_TRANSPORT_DATA_BLOCK_MASK (0x1)
498
499/** namespace features */
500/* thin provisioning */
501#define NVME_NS_DATA_NSFEAT_THIN_PROV_SHIFT (0)
502#define NVME_NS_DATA_NSFEAT_THIN_PROV_MASK (0x1)
503/* NAWUN, NAWUPF, and NACWU fields are valid */
504#define NVME_NS_DATA_NSFEAT_NA_FIELDS_SHIFT (1)
505#define NVME_NS_DATA_NSFEAT_NA_FIELDS_MASK (0x1)
506/* Deallocated or Unwritten Logical Block errors supported */
507#define NVME_NS_DATA_NSFEAT_DEALLOC_SHIFT (2)
508#define NVME_NS_DATA_NSFEAT_DEALLOC_MASK (0x1)
509/* NGUID and EUI64 fields are not reusable */
510#define NVME_NS_DATA_NSFEAT_NO_ID_REUSE_SHIFT (3)
511#define NVME_NS_DATA_NSFEAT_NO_ID_REUSE_MASK (0x1)
512/* NPWG, NPWA, NPDG, NPDA, and NOWS are valid */
513#define NVME_NS_DATA_NSFEAT_NPVALID_SHIFT (4)
514#define NVME_NS_DATA_NSFEAT_NPVALID_MASK (0x1)
515
516/** formatted lba size */
517#define NVME_NS_DATA_FLBAS_FORMAT_SHIFT (0)
518#define NVME_NS_DATA_FLBAS_FORMAT_MASK (0xF)
519#define NVME_NS_DATA_FLBAS_EXTENDED_SHIFT (4)
520#define NVME_NS_DATA_FLBAS_EXTENDED_MASK (0x1)
521
522/** metadata capabilities */
523/* metadata can be transferred as part of data prp list */
524#define NVME_NS_DATA_MC_EXTENDED_SHIFT (0)
525#define NVME_NS_DATA_MC_EXTENDED_MASK (0x1)
526/* metadata can be transferred with separate metadata pointer */
527#define NVME_NS_DATA_MC_POINTER_SHIFT (1)
528#define NVME_NS_DATA_MC_POINTER_MASK (0x1)
529
530/** end-to-end data protection capabilities */
531/* protection information type 1 */
532#define NVME_NS_DATA_DPC_PIT1_SHIFT (0)
533#define NVME_NS_DATA_DPC_PIT1_MASK (0x1)
534/* protection information type 2 */
535#define NVME_NS_DATA_DPC_PIT2_SHIFT (1)
536#define NVME_NS_DATA_DPC_PIT2_MASK (0x1)
537/* protection information type 3 */
538#define NVME_NS_DATA_DPC_PIT3_SHIFT (2)
539#define NVME_NS_DATA_DPC_PIT3_MASK (0x1)
540/* first eight bytes of metadata */
541#define NVME_NS_DATA_DPC_MD_START_SHIFT (3)
542#define NVME_NS_DATA_DPC_MD_START_MASK (0x1)
543/* last eight bytes of metadata */
544#define NVME_NS_DATA_DPC_MD_END_SHIFT (4)
545#define NVME_NS_DATA_DPC_MD_END_MASK (0x1)
546
547/** end-to-end data protection type settings */
548/* protection information type */
549#define NVME_NS_DATA_DPS_PIT_SHIFT (0)
550#define NVME_NS_DATA_DPS_PIT_MASK (0x7)
551/* 1 == protection info transferred at start of metadata */
552/* 0 == protection info transferred at end of metadata */
553#define NVME_NS_DATA_DPS_MD_START_SHIFT (3)
554#define NVME_NS_DATA_DPS_MD_START_MASK (0x1)
555
556/** Namespace Multi-path I/O and Namespace Sharing Capabilities */
557/* the namespace may be attached to two or more controllers */
558#define NVME_NS_DATA_NMIC_MAY_BE_SHARED_SHIFT (0)
559#define NVME_NS_DATA_NMIC_MAY_BE_SHARED_MASK (0x1)
560
561/** Reservation Capabilities */
562/* Persist Through Power Loss */
563#define NVME_NS_DATA_RESCAP_PTPL_SHIFT (0)
564#define NVME_NS_DATA_RESCAP_PTPL_MASK (0x1)
565/* supports the Write Exclusive */
566#define NVME_NS_DATA_RESCAP_WR_EX_SHIFT (1)
567#define NVME_NS_DATA_RESCAP_WR_EX_MASK (0x1)
568/* supports the Exclusive Access */
569#define NVME_NS_DATA_RESCAP_EX_AC_SHIFT (2)
570#define NVME_NS_DATA_RESCAP_EX_AC_MASK (0x1)
571/* supports the Write Exclusive – Registrants Only */
572#define NVME_NS_DATA_RESCAP_WR_EX_RO_SHIFT (3)
573#define NVME_NS_DATA_RESCAP_WR_EX_RO_MASK (0x1)
574/* supports the Exclusive Access - Registrants Only */
575#define NVME_NS_DATA_RESCAP_EX_AC_RO_SHIFT (4)
576#define NVME_NS_DATA_RESCAP_EX_AC_RO_MASK (0x1)
577/* supports the Write Exclusive – All Registrants */
578#define NVME_NS_DATA_RESCAP_WR_EX_AR_SHIFT (5)
579#define NVME_NS_DATA_RESCAP_WR_EX_AR_MASK (0x1)
580/* supports the Exclusive Access - All Registrants */
581#define NVME_NS_DATA_RESCAP_EX_AC_AR_SHIFT (6)
582#define NVME_NS_DATA_RESCAP_EX_AC_AR_MASK (0x1)
583/* Ignore Existing Key is used as defined in revision 1.3 or later */
584#define NVME_NS_DATA_RESCAP_IEKEY13_SHIFT (7)
585#define NVME_NS_DATA_RESCAP_IEKEY13_MASK (0x1)
586
587/** Format Progress Indicator */
588/* percentage of the Format NVM command that remains to be completed */
589#define NVME_NS_DATA_FPI_PERC_SHIFT (0)
590#define NVME_NS_DATA_FPI_PERC_MASK (0x7f)
591/* namespace supports the Format Progress Indicator */
592#define NVME_NS_DATA_FPI_SUPP_SHIFT (7)
593#define NVME_NS_DATA_FPI_SUPP_MASK (0x1)
594
595/** Deallocate Logical Block Features */
596/* deallocated logical block read behavior */
597#define NVME_NS_DATA_DLFEAT_READ_SHIFT (0)
598#define NVME_NS_DATA_DLFEAT_READ_MASK (0x07)
599#define NVME_NS_DATA_DLFEAT_READ_NR (0x00)
600#define NVME_NS_DATA_DLFEAT_READ_00 (0x01)
601#define NVME_NS_DATA_DLFEAT_READ_FF (0x02)
602/* supports the Deallocate bit in the Write Zeroes */
603#define NVME_NS_DATA_DLFEAT_DWZ_SHIFT (3)
604#define NVME_NS_DATA_DLFEAT_DWZ_MASK (0x01)
605/* Guard field for deallocated logical blocks is set to the CRC */
606#define NVME_NS_DATA_DLFEAT_GCRC_SHIFT (4)
607#define NVME_NS_DATA_DLFEAT_GCRC_MASK (0x01)
608
609/** lba format support */
610/* metadata size */
611#define NVME_NS_DATA_LBAF_MS_SHIFT (0)
612#define NVME_NS_DATA_LBAF_MS_MASK (0xFFFF)
613/* lba data size */
614#define NVME_NS_DATA_LBAF_LBADS_SHIFT (16)
615#define NVME_NS_DATA_LBAF_LBADS_MASK (0xFF)
616/* relative performance */
617#define NVME_NS_DATA_LBAF_RP_SHIFT (24)
618#define NVME_NS_DATA_LBAF_RP_MASK (0x3)
619
620enum nvme_critical_warning_state {
621 NVME_CRIT_WARN_ST_AVAILABLE_SPARE = 0x1,
622 NVME_CRIT_WARN_ST_TEMPERATURE = 0x2,
623 NVME_CRIT_WARN_ST_DEVICE_RELIABILITY = 0x4,
624 NVME_CRIT_WARN_ST_READ_ONLY = 0x8,
625 NVME_CRIT_WARN_ST_VOLATILE_MEMORY_BACKUP = 0x10,
626};
627#define NVME_CRIT_WARN_ST_RESERVED_MASK (0xE0)
628#define NVME_ASYNC_EVENT_NS_ATTRIBUTE (0x100)
629#define NVME_ASYNC_EVENT_FW_ACTIVATE (0x200)
630
631/* slot for current FW */
632#define NVME_FIRMWARE_PAGE_AFI_SLOT_SHIFT (0)
633#define NVME_FIRMWARE_PAGE_AFI_SLOT_MASK (0x7)
634
635/* Commands Supported and Effects */
636#define NVME_CE_PAGE_CSUP_SHIFT (0)
637#define NVME_CE_PAGE_CSUP_MASK (0x1)
638#define NVME_CE_PAGE_LBCC_SHIFT (1)
639#define NVME_CE_PAGE_LBCC_MASK (0x1)
640#define NVME_CE_PAGE_NCC_SHIFT (2)
641#define NVME_CE_PAGE_NCC_MASK (0x1)
642#define NVME_CE_PAGE_NIC_SHIFT (3)
643#define NVME_CE_PAGE_NIC_MASK (0x1)
644#define NVME_CE_PAGE_CCC_SHIFT (4)
645#define NVME_CE_PAGE_CCC_MASK (0x1)
646#define NVME_CE_PAGE_CSE_SHIFT (16)
647#define NVME_CE_PAGE_CSE_MASK (0x7)
648#define NVME_CE_PAGE_UUID_SHIFT (19)
649#define NVME_CE_PAGE_UUID_MASK (0x1)
650
651/* Sanitize Status */
652#define NVME_SS_PAGE_SSTAT_STATUS_SHIFT (0)
653#define NVME_SS_PAGE_SSTAT_STATUS_MASK (0x7)
654#define NVME_SS_PAGE_SSTAT_STATUS_NEVER (0)
655#define NVME_SS_PAGE_SSTAT_STATUS_COMPLETED (1)
656#define NVME_SS_PAGE_SSTAT_STATUS_INPROG (2)
657#define NVME_SS_PAGE_SSTAT_STATUS_FAILED (3)
658#define NVME_SS_PAGE_SSTAT_STATUS_COMPLETEDWD (4)
659#define NVME_SS_PAGE_SSTAT_PASSES_SHIFT (3)
660#define NVME_SS_PAGE_SSTAT_PASSES_MASK (0x1f)
661#define NVME_SS_PAGE_SSTAT_GDE_SHIFT (8)
662#define NVME_SS_PAGE_SSTAT_GDE_MASK (0x1)
663
664/* Features */
665/* Get Features */
666#define NVME_FEAT_GET_SEL_SHIFT (8)
667#define NVME_FEAT_GET_SEL_MASK (0x7)
668#define NVME_FEAT_GET_FID_SHIFT (0)
669#define NVME_FEAT_GET_FID_MASK (0xff)
670
671/* Set Features */
672#define NVME_FEAT_SET_SV_SHIFT (31)
673#define NVME_FEAT_SET_SV_MASK (0x1)
674#define NVME_FEAT_SET_FID_SHIFT (0)
675#define NVME_FEAT_SET_FID_MASK (0xff)
676
677/* Async Events */
678#define NVME_ASYNC_EVENT_TYPE_SHIFT (0)
679#define NVME_ASYNC_EVENT_TYPE_MASK (0x7)
680#define NVME_ASYNC_EVENT_INFO_SHIFT (8)
681#define NVME_ASYNC_EVENT_INFO_MASK (0xff)
682#define NVME_ASYNC_EVENT_LOG_PAGE_ID_SHIFT (16)
683#define NVME_ASYNC_EVENT_LOG_PAGE_ID_MASK (0xff)
684
685/* Helper macro to combine *_MASK and *_SHIFT defines */
686#define NVMEM(name) (name##_MASK << name##_SHIFT)
687
688/* Helper macro to extract value from x */
689#define NVMEV(name, x) (((x) >> name##_SHIFT) & name##_MASK)
690
691/* Helper macro to construct a field value */
692#define NVMEF(name, x) (((x) & name##_MASK) << name##_SHIFT)
693
694/* CC register SHN field values */
695enum shn_value {
696 NVME_SHN_NORMAL = 0x1,
697 NVME_SHN_ABRUPT = 0x2,
698};
699
700/* CSTS register SHST field values */
701enum shst_value {
702 NVME_SHST_NORMAL = 0x0,
703 NVME_SHST_OCCURRING = 0x1,
704 NVME_SHST_COMPLETE = 0x2,
705};
706
707struct nvme_registers {
708 uint32_t cap_lo; /* controller capabilities */
709 uint32_t cap_hi;
710 uint32_t vs; /* version */
711 uint32_t intms; /* interrupt mask set */
712 uint32_t intmc; /* interrupt mask clear */
713 uint32_t cc; /* controller configuration */
714 uint32_t reserved1;
715 uint32_t csts; /* controller status */
716 uint32_t nssr; /* NVM Subsystem Reset */
717 uint32_t aqa; /* admin queue attributes */
718 uint64_t asq; /* admin submission queue base addr */
719 uint64_t acq; /* admin completion queue base addr */
720 uint32_t cmbloc; /* Controller Memory Buffer Location */
721 uint32_t cmbsz; /* Controller Memory Buffer Size */
722 uint32_t bpinfo; /* Boot Partition Information */
723 uint32_t bprsel; /* Boot Partition Read Select */
724 uint64_t bpmbl; /* Boot Partition Memory Buffer Location */
725 uint64_t cmbmsc; /* Controller Memory Buffer Memory Space Control */
726 uint32_t cmbsts; /* Controller Memory Buffer Status */
727 uint32_t cmbebs; /* Controller Memory Buffer Elasticity Buffer Size */
728 uint32_t cmbswtp;/* Controller Memory Buffer Sustained Write Throughput */
729 uint32_t nssd; /* NVM Subsystem Shutdown */
730 uint32_t crto; /* Controller Ready Timeouts */
731 uint8_t reserved3[3476]; /* 6Ch - DFFh */
732 uint32_t pmrcap; /* Persistent Memory Capabilities */
733 uint32_t pmrctl; /* Persistent Memory Region Control */
734 uint32_t pmrsts; /* Persistent Memory Region Status */
735 uint32_t pmrebs; /* Persistent Memory Region Elasticity Buffer Size */
736 uint32_t pmrswtp; /* Persistent Memory Region Sustained Write Throughput */
737 uint32_t pmrmsc_lo; /* Persistent Memory Region Controller Memory Space Control */
738 uint32_t pmrmsc_hi;
739 uint8_t reserved4[484]; /* E1Ch - FFFh */
740 struct {
741 uint32_t sq_tdbl; /* submission queue tail doorbell */
742 uint32_t cq_hdbl; /* completion queue head doorbell */
743 } doorbell[1];
744};
745
746_Static_assert(sizeof(struct nvme_registers) == 0x1008, "bad size for nvme_registers");
747
748#define NVME_SGL_SUBTYPE_SHIFT (0)
749#define NVME_SGL_SUBTYPE_MASK (0xF)
750#define NVME_SGL_TYPE_SHIFT (4)
751#define NVME_SGL_TYPE_MASK (0xF)
752
753#define NVME_SGL_TYPE(type, subtype) \
754 ((subtype) << NVME_SGL_SUBTYPE_SHIFT | (type) << NVME_SGL_TYPE_SHIFT)
755
756enum nvme_sgl_type {
757 NVME_SGL_TYPE_DATA_BLOCK = 0x0,
758 NVME_SGL_TYPE_BIT_BUCKET = 0x1,
759 NVME_SGL_TYPE_SEGMENT = 0x2,
760 NVME_SGL_TYPE_LAST_SEGMENT = 0x3,
761 NVME_SGL_TYPE_KEYED_DATA_BLOCK = 0x4,
762 NVME_SGL_TYPE_TRANSPORT_DATA_BLOCK = 0x5,
763};
764
765enum nvme_sgl_subtype {
766 NVME_SGL_SUBTYPE_ADDRESS = 0x0,
767 NVME_SGL_SUBTYPE_OFFSET = 0x1,
768 NVME_SGL_SUBTYPE_TRANSPORT = 0xa,
769};
770
771struct nvme_sgl_descriptor {
772 uint64_t address;
773 uint32_t length;
774 uint8_t reserved[3];
775 uint8_t type;
776};
777
778_Static_assert(sizeof(struct nvme_sgl_descriptor) == 16, "bad size for nvme_sgl_descriptor");
779
780struct nvme_command {
781 /* dword 0 */
782 uint8_t opc; /* opcode */
783 uint8_t fuse; /* fused operation */
784 uint16_t cid; /* command identifier */
785
786 /* dword 1 */
787 uint32_t nsid; /* namespace identifier */
788
789 /* dword 2-3 */
790 uint32_t rsvd2;
791 uint32_t rsvd3;
792
793 /* dword 4-5 */
794 uint64_t mptr; /* metadata pointer */
795
796 /* dword 6-9 */
797 union {
798 struct {
799 uint64_t prp1; /* prp entry 1 */
800 uint64_t prp2; /* prp entry 2 */
801 };
802 struct nvme_sgl_descriptor sgl;
803 };
804
805 /* dword 10-15 */
806 uint32_t cdw10; /* command-specific */
807 uint32_t cdw11; /* command-specific */
808 uint32_t cdw12; /* command-specific */
809 uint32_t cdw13; /* command-specific */
810 uint32_t cdw14; /* command-specific */
811 uint32_t cdw15; /* command-specific */
812};
813
814_Static_assert(sizeof(struct nvme_command) == 16 * 4, "bad size for nvme_command");
815
816struct nvme_completion {
817 /* dword 0 */
818 uint32_t cdw0; /* command-specific */
819
820 /* dword 1 */
821 uint32_t rsvd1;
822
823 /* dword 2 */
824 uint16_t sqhd; /* submission queue head pointer */
825 uint16_t sqid; /* submission queue identifier */
826
827 /* dword 3 */
828 uint16_t cid; /* command identifier */
829 uint16_t status;
830} __aligned(8); /* riscv: nvme_qpair_process_completions has better code gen */
831
832_Static_assert(sizeof(struct nvme_completion) == 4 * 4, "bad size for nvme_completion");
833
834struct nvme_dsm_range {
835 uint32_t attributes;
836 uint32_t length;
837 uint64_t starting_lba;
838};
839
840/* Largest DSM Trim that can be done */
841#define NVME_MAX_DSM_TRIM 4096
842
843_Static_assert(sizeof(struct nvme_dsm_range) == 16, "bad size for nvme_dsm_ranage");
844
845/* status code types */
846enum nvme_status_code_type {
847 NVME_SCT_GENERIC = 0x0,
848 NVME_SCT_COMMAND_SPECIFIC = 0x1,
849 NVME_SCT_MEDIA_ERROR = 0x2,
850 NVME_SCT_PATH_RELATED = 0x3,
851 /* 0x3-0x6 - reserved */
852 NVME_SCT_VENDOR_SPECIFIC = 0x7,
853};
854
855/* generic command status codes */
856enum nvme_generic_command_status_code {
857 NVME_SC_SUCCESS = 0x00,
858 NVME_SC_INVALID_OPCODE = 0x01,
859 NVME_SC_INVALID_FIELD = 0x02,
860 NVME_SC_COMMAND_ID_CONFLICT = 0x03,
861 NVME_SC_DATA_TRANSFER_ERROR = 0x04,
862 NVME_SC_ABORTED_POWER_LOSS = 0x05,
863 NVME_SC_INTERNAL_DEVICE_ERROR = 0x06,
864 NVME_SC_ABORTED_BY_REQUEST = 0x07,
865 NVME_SC_ABORTED_SQ_DELETION = 0x08,
866 NVME_SC_ABORTED_FAILED_FUSED = 0x09,
867 NVME_SC_ABORTED_MISSING_FUSED = 0x0a,
868 NVME_SC_INVALID_NAMESPACE_OR_FORMAT = 0x0b,
869 NVME_SC_COMMAND_SEQUENCE_ERROR = 0x0c,
870 NVME_SC_INVALID_SGL_SEGMENT_DESCR = 0x0d,
871 NVME_SC_INVALID_NUMBER_OF_SGL_DESCR = 0x0e,
872 NVME_SC_DATA_SGL_LENGTH_INVALID = 0x0f,
873 NVME_SC_METADATA_SGL_LENGTH_INVALID = 0x10,
874 NVME_SC_SGL_DESCRIPTOR_TYPE_INVALID = 0x11,
875 NVME_SC_INVALID_USE_OF_CMB = 0x12,
876 NVME_SC_PRP_OFFET_INVALID = 0x13,
877 NVME_SC_ATOMIC_WRITE_UNIT_EXCEEDED = 0x14,
878 NVME_SC_OPERATION_DENIED = 0x15,
879 NVME_SC_SGL_OFFSET_INVALID = 0x16,
880 /* 0x17 - reserved */
881 NVME_SC_HOST_ID_INCONSISTENT_FORMAT = 0x18,
882 NVME_SC_KEEP_ALIVE_TIMEOUT_EXPIRED = 0x19,
883 NVME_SC_KEEP_ALIVE_TIMEOUT_INVALID = 0x1a,
884 NVME_SC_ABORTED_DUE_TO_PREEMPT = 0x1b,
885 NVME_SC_SANITIZE_FAILED = 0x1c,
886 NVME_SC_SANITIZE_IN_PROGRESS = 0x1d,
887 NVME_SC_SGL_DATA_BLOCK_GRAN_INVALID = 0x1e,
888 NVME_SC_NOT_SUPPORTED_IN_CMB = 0x1f,
889 NVME_SC_NAMESPACE_IS_WRITE_PROTECTED = 0x20,
890 NVME_SC_COMMAND_INTERRUPTED = 0x21,
891 NVME_SC_TRANSIENT_TRANSPORT_ERROR = 0x22,
892
893 NVME_SC_LBA_OUT_OF_RANGE = 0x80,
894 NVME_SC_CAPACITY_EXCEEDED = 0x81,
895 NVME_SC_NAMESPACE_NOT_READY = 0x82,
896 NVME_SC_RESERVATION_CONFLICT = 0x83,
897 NVME_SC_FORMAT_IN_PROGRESS = 0x84,
898};
899
900/* command specific status codes */
901enum nvme_command_specific_status_code {
902 NVME_SC_COMPLETION_QUEUE_INVALID = 0x00,
903 NVME_SC_INVALID_QUEUE_IDENTIFIER = 0x01,
904 NVME_SC_MAXIMUM_QUEUE_SIZE_EXCEEDED = 0x02,
905 NVME_SC_ABORT_COMMAND_LIMIT_EXCEEDED = 0x03,
906 /* 0x04 - reserved */
907 NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED = 0x05,
908 NVME_SC_INVALID_FIRMWARE_SLOT = 0x06,
909 NVME_SC_INVALID_FIRMWARE_IMAGE = 0x07,
910 NVME_SC_INVALID_INTERRUPT_VECTOR = 0x08,
911 NVME_SC_INVALID_LOG_PAGE = 0x09,
912 NVME_SC_INVALID_FORMAT = 0x0a,
913 NVME_SC_FIRMWARE_REQUIRES_RESET = 0x0b,
914 NVME_SC_INVALID_QUEUE_DELETION = 0x0c,
915 NVME_SC_FEATURE_NOT_SAVEABLE = 0x0d,
916 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x0e,
917 NVME_SC_FEATURE_NOT_NS_SPECIFIC = 0x0f,
918 NVME_SC_FW_ACT_REQUIRES_NVMS_RESET = 0x10,
919 NVME_SC_FW_ACT_REQUIRES_RESET = 0x11,
920 NVME_SC_FW_ACT_REQUIRES_TIME = 0x12,
921 NVME_SC_FW_ACT_PROHIBITED = 0x13,
922 NVME_SC_OVERLAPPING_RANGE = 0x14,
923 NVME_SC_NS_INSUFFICIENT_CAPACITY = 0x15,
924 NVME_SC_NS_ID_UNAVAILABLE = 0x16,
925 /* 0x17 - reserved */
926 NVME_SC_NS_ALREADY_ATTACHED = 0x18,
927 NVME_SC_NS_IS_PRIVATE = 0x19,
928 NVME_SC_NS_NOT_ATTACHED = 0x1a,
929 NVME_SC_THIN_PROV_NOT_SUPPORTED = 0x1b,
930 NVME_SC_CTRLR_LIST_INVALID = 0x1c,
931 NVME_SC_SELF_TEST_IN_PROGRESS = 0x1d,
932 NVME_SC_BOOT_PART_WRITE_PROHIB = 0x1e,
933 NVME_SC_INVALID_CTRLR_ID = 0x1f,
934 NVME_SC_INVALID_SEC_CTRLR_STATE = 0x20,
935 NVME_SC_INVALID_NUM_OF_CTRLR_RESRC = 0x21,
936 NVME_SC_INVALID_RESOURCE_ID = 0x22,
937 NVME_SC_SANITIZE_PROHIBITED_WPMRE = 0x23,
938 NVME_SC_ANA_GROUP_ID_INVALID = 0x24,
939 NVME_SC_ANA_ATTACH_FAILED = 0x25,
940
941 NVME_SC_CONFLICTING_ATTRIBUTES = 0x80,
942 NVME_SC_INVALID_PROTECTION_INFO = 0x81,
943 NVME_SC_ATTEMPTED_WRITE_TO_RO_PAGE = 0x82,
944};
945
946/* media error status codes */
947enum nvme_media_error_status_code {
948 NVME_SC_WRITE_FAULTS = 0x80,
949 NVME_SC_UNRECOVERED_READ_ERROR = 0x81,
950 NVME_SC_GUARD_CHECK_ERROR = 0x82,
951 NVME_SC_APPLICATION_TAG_CHECK_ERROR = 0x83,
952 NVME_SC_REFERENCE_TAG_CHECK_ERROR = 0x84,
953 NVME_SC_COMPARE_FAILURE = 0x85,
954 NVME_SC_ACCESS_DENIED = 0x86,
955 NVME_SC_DEALLOCATED_OR_UNWRITTEN = 0x87,
956};
957
958/* path related status codes */
959enum nvme_path_related_status_code {
960 NVME_SC_INTERNAL_PATH_ERROR = 0x00,
961 NVME_SC_ASYMMETRIC_ACCESS_PERSISTENT_LOSS = 0x01,
962 NVME_SC_ASYMMETRIC_ACCESS_INACCESSIBLE = 0x02,
963 NVME_SC_ASYMMETRIC_ACCESS_TRANSITION = 0x03,
964 NVME_SC_CONTROLLER_PATHING_ERROR = 0x60,
965 NVME_SC_HOST_PATHING_ERROR = 0x70,
966 NVME_SC_COMMAND_ABORTED_BY_HOST = 0x71,
967};
968
969/* admin opcodes */
970enum nvme_admin_opcode {
971 NVME_OPC_DELETE_IO_SQ = 0x00,
972 NVME_OPC_CREATE_IO_SQ = 0x01,
973 NVME_OPC_GET_LOG_PAGE = 0x02,
974 /* 0x03 - reserved */
975 NVME_OPC_DELETE_IO_CQ = 0x04,
976 NVME_OPC_CREATE_IO_CQ = 0x05,
977 NVME_OPC_IDENTIFY = 0x06,
978 /* 0x07 - reserved */
979 NVME_OPC_ABORT = 0x08,
980 NVME_OPC_SET_FEATURES = 0x09,
981 NVME_OPC_GET_FEATURES = 0x0a,
982 /* 0x0b - reserved */
983 NVME_OPC_ASYNC_EVENT_REQUEST = 0x0c,
984 NVME_OPC_NAMESPACE_MANAGEMENT = 0x0d,
985 /* 0x0e-0x0f - reserved */
986 NVME_OPC_FIRMWARE_ACTIVATE = 0x10,
987 NVME_OPC_FIRMWARE_IMAGE_DOWNLOAD = 0x11,
988 /* 0x12-0x13 - reserved */
989 NVME_OPC_DEVICE_SELF_TEST = 0x14,
990 NVME_OPC_NAMESPACE_ATTACHMENT = 0x15,
991 /* 0x16-0x17 - reserved */
992 NVME_OPC_KEEP_ALIVE = 0x18,
993 NVME_OPC_DIRECTIVE_SEND = 0x19,
994 NVME_OPC_DIRECTIVE_RECEIVE = 0x1a,
995 /* 0x1b - reserved */
996 NVME_OPC_VIRTUALIZATION_MANAGEMENT = 0x1c,
997 NVME_OPC_NVME_MI_SEND = 0x1d,
998 NVME_OPC_NVME_MI_RECEIVE = 0x1e,
999 /* 0x1f - reserved */
1000 NVME_OPC_CAPACITY_MANAGEMENT = 0x20,
1001 /* 0x21-0x23 - reserved */
1002 NVME_OPC_LOCKDOWN = 0x24,
1003 /* 0x25-0x7b - reserved */
1004 NVME_OPC_DOORBELL_BUFFER_CONFIG = 0x7c,
1005 /* 0x7d-0x7e - reserved */
1006 NVME_OPC_FABRICS_COMMANDS = 0x7f,
1007
1008 NVME_OPC_FORMAT_NVM = 0x80,
1009 NVME_OPC_SECURITY_SEND = 0x81,
1010 NVME_OPC_SECURITY_RECEIVE = 0x82,
1011 /* 0x83 - reserved */
1012 NVME_OPC_SANITIZE = 0x84,
1013 /* 0x85 - reserved */
1014 NVME_OPC_GET_LBA_STATUS = 0x86,
1015};
1016
1017/* nvme nvm opcodes */
1018enum nvme_nvm_opcode {
1019 NVME_OPC_FLUSH = 0x00,
1020 NVME_OPC_WRITE = 0x01,
1021 NVME_OPC_READ = 0x02,
1022 /* 0x03 - reserved */
1023 NVME_OPC_WRITE_UNCORRECTABLE = 0x04,
1024 NVME_OPC_COMPARE = 0x05,
1025 /* 0x06-0x07 - reserved */
1026 NVME_OPC_WRITE_ZEROES = 0x08,
1027 NVME_OPC_DATASET_MANAGEMENT = 0x09,
1028 /* 0x0a-0x0b - reserved */
1029 NVME_OPC_VERIFY = 0x0c,
1030 NVME_OPC_RESERVATION_REGISTER = 0x0d,
1031 NVME_OPC_RESERVATION_REPORT = 0x0e,
1032 /* 0x0f-0x10 - reserved */
1033 NVME_OPC_RESERVATION_ACQUIRE = 0x11,
1034 /* 0x12-0x14 - reserved */
1035 NVME_OPC_RESERVATION_RELEASE = 0x15,
1036 /* 0x16-0x18 - reserved */
1037 NVME_OPC_COPY = 0x19,
1038};
1039
1040enum nvme_feature {
1041 /* 0x00 - reserved */
1042 NVME_FEAT_ARBITRATION = 0x01,
1043 NVME_FEAT_POWER_MANAGEMENT = 0x02,
1044 NVME_FEAT_LBA_RANGE_TYPE = 0x03,
1045 NVME_FEAT_TEMPERATURE_THRESHOLD = 0x04,
1046 NVME_FEAT_ERROR_RECOVERY = 0x05,
1047 NVME_FEAT_VOLATILE_WRITE_CACHE = 0x06,
1048 NVME_FEAT_NUMBER_OF_QUEUES = 0x07,
1049 NVME_FEAT_INTERRUPT_COALESCING = 0x08,
1050 NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION = 0x09,
1051 NVME_FEAT_WRITE_ATOMICITY = 0x0A,
1052 NVME_FEAT_ASYNC_EVENT_CONFIGURATION = 0x0B,
1053 NVME_FEAT_AUTONOMOUS_POWER_STATE_TRANSITION = 0x0C,
1054 NVME_FEAT_HOST_MEMORY_BUFFER = 0x0D,
1055 NVME_FEAT_TIMESTAMP = 0x0E,
1056 NVME_FEAT_KEEP_ALIVE_TIMER = 0x0F,
1057 NVME_FEAT_HOST_CONTROLLED_THERMAL_MGMT = 0x10,
1058 NVME_FEAT_NON_OP_POWER_STATE_CONFIG = 0x11,
1059 NVME_FEAT_READ_RECOVERY_LEVEL_CONFIG = 0x12,
1060 NVME_FEAT_PREDICTABLE_LATENCY_MODE_CONFIG = 0x13,
1061 NVME_FEAT_PREDICTABLE_LATENCY_MODE_WINDOW = 0x14,
1062 NVME_FEAT_LBA_STATUS_INFORMATION_ATTRIBUTES = 0x15,
1063 NVME_FEAT_HOST_BEHAVIOR_SUPPORT = 0x16,
1064 NVME_FEAT_SANITIZE_CONFIG = 0x17,
1065 NVME_FEAT_ENDURANCE_GROUP_EVENT_CONFIGURATION = 0x18,
1066 /* 0x19-0x77 - reserved */
1067 /* 0x78-0x7f - NVMe Management Interface */
1068 NVME_FEAT_SOFTWARE_PROGRESS_MARKER = 0x80,
1069 NVME_FEAT_HOST_IDENTIFIER = 0x81,
1070 NVME_FEAT_RESERVATION_NOTIFICATION_MASK = 0x82,
1071 NVME_FEAT_RESERVATION_PERSISTENCE = 0x83,
1072 NVME_FEAT_NAMESPACE_WRITE_PROTECTION_CONFIG = 0x84,
1073 /* 0x85-0xBF - command set specific (reserved) */
1074 /* 0xC0-0xFF - vendor specific */
1075};
1076
1077enum nvme_dsm_attribute {
1078 NVME_DSM_ATTR_INTEGRAL_READ = 0x1,
1079 NVME_DSM_ATTR_INTEGRAL_WRITE = 0x2,
1080 NVME_DSM_ATTR_DEALLOCATE = 0x4,
1081};
1082
1083enum nvme_activate_action {
1084 NVME_AA_REPLACE_NO_ACTIVATE = 0x0,
1085 NVME_AA_REPLACE_ACTIVATE = 0x1,
1086 NVME_AA_ACTIVATE = 0x2,
1087};
1088
1089struct nvme_power_state {
1090 /** Maximum Power */
1091 uint16_t mp; /* Maximum Power */
1092 uint8_t ps_rsvd1;
1093 uint8_t mps_nops; /* Max Power Scale, Non-Operational State */
1094
1095 uint32_t enlat; /* Entry Latency */
1096 uint32_t exlat; /* Exit Latency */
1097
1098 uint8_t rrt; /* Relative Read Throughput */
1099 uint8_t rrl; /* Relative Read Latency */
1100 uint8_t rwt; /* Relative Write Throughput */
1101 uint8_t rwl; /* Relative Write Latency */
1102
1103 uint16_t idlp; /* Idle Power */
1104 uint8_t ips; /* Idle Power Scale */
1105 uint8_t ps_rsvd8;
1106
1107 uint16_t actp; /* Active Power */
1108 uint8_t apw_aps; /* Active Power Workload, Active Power Scale */
1109 uint8_t ps_rsvd10[9];
1110} __packed;
1111
1112_Static_assert(sizeof(struct nvme_power_state) == 32, "bad size for nvme_power_state");
1113
1114#define NVME_SERIAL_NUMBER_LENGTH 20
1115#define NVME_MODEL_NUMBER_LENGTH 40
1116#define NVME_FIRMWARE_REVISION_LENGTH 8
1117
1118struct nvme_controller_data {
1119 /* bytes 0-255: controller capabilities and features */
1120
1121 /** pci vendor id */
1122 uint16_t vid;
1123
1124 /** pci subsystem vendor id */
1125 uint16_t ssvid;
1126
1127 /** serial number */
1128 uint8_t sn[NVME_SERIAL_NUMBER_LENGTH];
1129
1130 /** model number */
1131 uint8_t mn[NVME_MODEL_NUMBER_LENGTH];
1132
1133 /** firmware revision */
1134 uint8_t fr[NVME_FIRMWARE_REVISION_LENGTH];
1135
1136 /** recommended arbitration burst */
1137 uint8_t rab;
1138
1139 /** ieee oui identifier */
1140 uint8_t ieee[3];
1141
1142 /** multi-interface capabilities */
1143 uint8_t mic;
1144
1145 /** maximum data transfer size */
1146 uint8_t mdts;
1147
1148 /** Controller ID */
1149 uint16_t ctrlr_id;
1150
1151 /** Version */
1152 uint32_t ver;
1153
1154 /** RTD3 Resume Latency */
1155 uint32_t rtd3r;
1156
1157 /** RTD3 Enter Latency */
1158 uint32_t rtd3e;
1159
1160 /** Optional Asynchronous Events Supported */
1161 uint32_t oaes; /* bitfield really */
1162
1163 /** Controller Attributes */
1164 uint32_t ctratt; /* bitfield really */
1165
1166 /** Read Recovery Levels Supported */
1167 uint16_t rrls;
1168
1169 uint8_t reserved1[9];
1170
1171 /** Controller Type */
1172 uint8_t cntrltype;
1173
1174 /** FRU Globally Unique Identifier */
1175 uint8_t fguid[16];
1176
1177 /** Command Retry Delay Time 1 */
1178 uint16_t crdt1;
1179
1180 /** Command Retry Delay Time 2 */
1181 uint16_t crdt2;
1182
1183 /** Command Retry Delay Time 3 */
1184 uint16_t crdt3;
1185
1186 uint8_t reserved2[122];
1187
1188 /* bytes 256-511: admin command set attributes */
1189
1190 /** optional admin command support */
1191 uint16_t oacs;
1192
1193 /** abort command limit */
1194 uint8_t acl;
1195
1196 /** asynchronous event request limit */
1197 uint8_t aerl;
1198
1199 /** firmware updates */
1200 uint8_t frmw;
1201
1202 /** log page attributes */
1203 uint8_t lpa;
1204
1205 /** error log page entries */
1206 uint8_t elpe;
1207
1208 /** number of power states supported */
1209 uint8_t npss;
1210
1211 /** admin vendor specific command configuration */
1212 uint8_t avscc;
1213
1214 /** Autonomous Power State Transition Attributes */
1215 uint8_t apsta;
1216
1217 /** Warning Composite Temperature Threshold */
1218 uint16_t wctemp;
1219
1220 /** Critical Composite Temperature Threshold */
1221 uint16_t cctemp;
1222
1223 /** Maximum Time for Firmware Activation */
1224 uint16_t mtfa;
1225
1226 /** Host Memory Buffer Preferred Size */
1227 uint32_t hmpre;
1228
1229 /** Host Memory Buffer Minimum Size */
1230 uint32_t hmmin;
1231
1232 /** Name space capabilities */
1233 struct {
1234 /* if nsmgmt, report tnvmcap and unvmcap */
1235 uint8_t tnvmcap[16];
1236 uint8_t unvmcap[16];
1237 } __packed untncap;
1238
1239 /** Replay Protected Memory Block Support */
1240 uint32_t rpmbs; /* Really a bitfield */
1241
1242 /** Extended Device Self-test Time */
1243 uint16_t edstt;
1244
1245 /** Device Self-test Options */
1246 uint8_t dsto; /* Really a bitfield */
1247
1248 /** Firmware Update Granularity */
1249 uint8_t fwug;
1250
1251 /** Keep Alive Support */
1252 uint16_t kas;
1253
1254 /** Host Controlled Thermal Management Attributes */
1255 uint16_t hctma; /* Really a bitfield */
1256
1257 /** Minimum Thermal Management Temperature */
1258 uint16_t mntmt;
1259
1260 /** Maximum Thermal Management Temperature */
1261 uint16_t mxtmt;
1262
1263 /** Sanitize Capabilities */
1264 uint32_t sanicap; /* Really a bitfield */
1265
1266 /** Host Memory Buffer Minimum Descriptor Entry Size */
1267 uint32_t hmminds;
1268
1269 /** Host Memory Maximum Descriptors Entries */
1270 uint16_t hmmaxd;
1271
1272 /** NVM Set Identifier Maximum */
1273 uint16_t nsetidmax;
1274
1275 /** Endurance Group Identifier Maximum */
1276 uint16_t endgidmax;
1277
1278 /** ANA Transition Time */
1279 uint8_t anatt;
1280
1281 /** Asymmetric Namespace Access Capabilities */
1282 uint8_t anacap;
1283
1284 /** ANA Group Identifier Maximum */
1285 uint32_t anagrpmax;
1286
1287 /** Number of ANA Group Identifiers */
1288 uint32_t nanagrpid;
1289
1290 /** Persistent Event Log Size */
1291 uint32_t pels;
1292
1293 uint8_t reserved3[156];
1294 /* bytes 512-703: nvm command set attributes */
1295
1296 /** submission queue entry size */
1297 uint8_t sqes;
1298
1299 /** completion queue entry size */
1300 uint8_t cqes;
1301
1302 /** Maximum Outstanding Commands */
1303 uint16_t maxcmd;
1304
1305 /** number of namespaces */
1306 uint32_t nn;
1307
1308 /** optional nvm command support */
1309 uint16_t oncs;
1310
1311 /** fused operation support */
1312 uint16_t fuses;
1313
1314 /** format nvm attributes */
1315 uint8_t fna;
1316
1317 /** volatile write cache */
1318 uint8_t vwc;
1319
1320 /** Atomic Write Unit Normal */
1321 uint16_t awun;
1322
1323 /** Atomic Write Unit Power Fail */
1324 uint16_t awupf;
1325
1326 /** NVM Vendor Specific Command Configuration */
1327 uint8_t nvscc;
1328
1329 /** Namespace Write Protection Capabilities */
1330 uint8_t nwpc;
1331
1332 /** Atomic Compare & Write Unit */
1333 uint16_t acwu;
1334 uint16_t reserved6;
1335
1336 /** SGL Support */
1337 uint32_t sgls;
1338
1339 /** Maximum Number of Allowed Namespaces */
1340 uint32_t mnan;
1341
1342 /* bytes 540-767: Reserved */
1343 uint8_t reserved7[224];
1344
1345 /** NVM Subsystem NVMe Qualified Name */
1346 uint8_t subnqn[256];
1347
1348 /* bytes 1024-1791: Reserved */
1349 uint8_t reserved8[768];
1350
1351 /* bytes 1792-2047: NVMe over Fabrics specification */
1352 uint32_t ioccsz;
1353 uint32_t iorcsz;
1354 uint16_t icdoff;
1355 uint8_t fcatt;
1356 uint8_t msdbd;
1357 uint16_t ofcs;
1358 uint8_t reserved9[242];
1359
1360 /* bytes 2048-3071: power state descriptors */
1361 struct nvme_power_state power_state[32];
1362
1363 /* bytes 3072-4095: vendor specific */
1364 uint8_t vs[1024];
1365} __packed __aligned(4);
1366
1367_Static_assert(sizeof(struct nvme_controller_data) == 4096, "bad size for nvme_controller_data");
1368
1369struct nvme_namespace_data {
1370 /** namespace size */
1371 uint64_t nsze;
1372
1373 /** namespace capacity */
1374 uint64_t ncap;
1375
1376 /** namespace utilization */
1377 uint64_t nuse;
1378
1379 /** namespace features */
1380 uint8_t nsfeat;
1381
1382 /** number of lba formats */
1383 uint8_t nlbaf;
1384
1385 /** formatted lba size */
1386 uint8_t flbas;
1387
1388 /** metadata capabilities */
1389 uint8_t mc;
1390
1391 /** end-to-end data protection capabilities */
1392 uint8_t dpc;
1393
1394 /** end-to-end data protection type settings */
1395 uint8_t dps;
1396
1397 /** Namespace Multi-path I/O and Namespace Sharing Capabilities */
1398 uint8_t nmic;
1399
1400 /** Reservation Capabilities */
1401 uint8_t rescap;
1402
1403 /** Format Progress Indicator */
1404 uint8_t fpi;
1405
1406 /** Deallocate Logical Block Features */
1407 uint8_t dlfeat;
1408
1409 /** Namespace Atomic Write Unit Normal */
1410 uint16_t nawun;
1411
1412 /** Namespace Atomic Write Unit Power Fail */
1413 uint16_t nawupf;
1414
1415 /** Namespace Atomic Compare & Write Unit */
1416 uint16_t nacwu;
1417
1418 /** Namespace Atomic Boundary Size Normal */
1419 uint16_t nabsn;
1420
1421 /** Namespace Atomic Boundary Offset */
1422 uint16_t nabo;
1423
1424 /** Namespace Atomic Boundary Size Power Fail */
1425 uint16_t nabspf;
1426
1427 /** Namespace Optimal IO Boundary */
1428 uint16_t noiob;
1429
1430 /** NVM Capacity */
1431 uint8_t nvmcap[16];
1432
1433 /** Namespace Preferred Write Granularity */
1434 uint16_t npwg;
1435
1436 /** Namespace Preferred Write Alignment */
1437 uint16_t npwa;
1438
1439 /** Namespace Preferred Deallocate Granularity */
1440 uint16_t npdg;
1441
1442 /** Namespace Preferred Deallocate Alignment */
1443 uint16_t npda;
1444
1445 /** Namespace Optimal Write Size */
1446 uint16_t nows;
1447
1448 /* bytes 74-91: Reserved */
1449 uint8_t reserved5[18];
1450
1451 /** ANA Group Identifier */
1452 uint32_t anagrpid;
1453
1454 /* bytes 96-98: Reserved */
1455 uint8_t reserved6[3];
1456
1457 /** Namespace Attributes */
1458 uint8_t nsattr;
1459
1460 /** NVM Set Identifier */
1461 uint16_t nvmsetid;
1462
1463 /** Endurance Group Identifier */
1464 uint16_t endgid;
1465
1466 /** Namespace Globally Unique Identifier */
1467 uint8_t nguid[16];
1468
1469 /** IEEE Extended Unique Identifier */
1470 uint8_t eui64[8];
1471
1472 /** lba format support */
1473 uint32_t lbaf[16];
1474
1475 uint8_t reserved7[192];
1476
1477 uint8_t vendor_specific[3712];
1478} __packed __aligned(4);
1479
1480_Static_assert(sizeof(struct nvme_namespace_data) == 4096, "bad size for nvme_namepsace_data");
1481
1482enum nvme_log_page {
1483 /* 0x00 - reserved */
1484 NVME_LOG_ERROR = 0x01,
1485 NVME_LOG_HEALTH_INFORMATION = 0x02,
1486 NVME_LOG_FIRMWARE_SLOT = 0x03,
1487 NVME_LOG_CHANGED_NAMESPACE = 0x04,
1488 NVME_LOG_COMMAND_EFFECT = 0x05,
1489 NVME_LOG_DEVICE_SELF_TEST = 0x06,
1490 NVME_LOG_TELEMETRY_HOST_INITIATED = 0x07,
1491 NVME_LOG_TELEMETRY_CONTROLLER_INITIATED = 0x08,
1492 NVME_LOG_ENDURANCE_GROUP_INFORMATION = 0x09,
1493 NVME_LOG_PREDICTABLE_LATENCY_PER_NVM_SET = 0x0a,
1494 NVME_LOG_PREDICTABLE_LATENCY_EVENT_AGGREGATE = 0x0b,
1495 NVME_LOG_ASYMMETRIC_NAMESPACE_ACCESS = 0x0c,
1496 NVME_LOG_PERSISTENT_EVENT_LOG = 0x0d,
1497 NVME_LOG_LBA_STATUS_INFORMATION = 0x0e,
1498 NVME_LOG_ENDURANCE_GROUP_EVENT_AGGREGATE = 0x0f,
1499 NVME_LOG_DISCOVERY = 0x70,
1500 /* 0x06-0x7F - reserved */
1501 /* 0x80-0xBF - I/O command set specific */
1502 NVME_LOG_RES_NOTIFICATION = 0x80,
1503 NVME_LOG_SANITIZE_STATUS = 0x81,
1504 /* 0x82-0xBF - reserved */
1505 /* 0xC0-0xFF - vendor specific */
1506
1507 /*
1508 * The following are Intel Specific log pages, but they seem
1509 * to be widely implemented.
1510 */
1511 INTEL_LOG_READ_LAT_LOG = 0xc1,
1512 INTEL_LOG_WRITE_LAT_LOG = 0xc2,
1513 INTEL_LOG_TEMP_STATS = 0xc5,
1514 INTEL_LOG_ADD_SMART = 0xca,
1515 INTEL_LOG_DRIVE_MKT_NAME = 0xdd,
1516
1517 /*
1518 * HGST log page, with lots ofs sub pages.
1519 */
1520 HGST_INFO_LOG = 0xc1,
1521};
1522
1523struct nvme_error_information_entry {
1524 uint64_t error_count;
1525 uint16_t sqid;
1526 uint16_t cid;
1527 uint16_t status;
1528 uint16_t error_location;
1529 uint64_t lba;
1530 uint32_t nsid;
1531 uint8_t vendor_specific;
1532 uint8_t trtype;
1533 uint16_t reserved30;
1534 uint64_t csi;
1535 uint16_t ttsi;
1536 uint8_t reserved[22];
1537} __packed __aligned(4);
1538
1539_Static_assert(sizeof(struct nvme_error_information_entry) == 64, "bad size for nvme_error_information_entry");
1540
1541struct nvme_health_information_page {
1542 uint8_t critical_warning;
1543 uint16_t temperature;
1544 uint8_t available_spare;
1545 uint8_t available_spare_threshold;
1546 uint8_t percentage_used;
1547
1548 uint8_t reserved[26];
1549
1550 /*
1551 * Note that the following are 128-bit values, but are
1552 * defined as an array of 2 64-bit values.
1553 */
1554 /* Data Units Read is always in 512-byte units. */
1555 uint64_t data_units_read[2];
1556 /* Data Units Written is always in 512-byte units. */
1557 uint64_t data_units_written[2];
1558 /* For NVM command set, this includes Compare commands. */
1559 uint64_t host_read_commands[2];
1560 uint64_t host_write_commands[2];
1561 /* Controller Busy Time is reported in minutes. */
1562 uint64_t controller_busy_time[2];
1563 uint64_t power_cycles[2];
1564 uint64_t power_on_hours[2];
1565 uint64_t unsafe_shutdowns[2];
1566 uint64_t media_errors[2];
1567 uint64_t num_error_info_log_entries[2];
1568 uint32_t warning_temp_time;
1569 uint32_t error_temp_time;
1570 uint16_t temp_sensor[8];
1571 /* Thermal Management Temperature 1 Transition Count */
1572 uint32_t tmt1tc;
1573 /* Thermal Management Temperature 2 Transition Count */
1574 uint32_t tmt2tc;
1575 /* Total Time For Thermal Management Temperature 1 */
1576 uint32_t ttftmt1;
1577 /* Total Time For Thermal Management Temperature 2 */
1578 uint32_t ttftmt2;
1579
1580 uint8_t reserved2[280];
1581} __packed __aligned(4);
1582
1583_Static_assert(sizeof(struct nvme_health_information_page) == 512, "bad size for nvme_health_information_page");
1584
1585struct nvme_firmware_page {
1586 uint8_t afi;
1587 uint8_t reserved[7];
1588 /* revisions for 7 slots */
1589 uint8_t revision[7][NVME_FIRMWARE_REVISION_LENGTH];
1590 uint8_t reserved2[448];
1591} __packed __aligned(4);
1592
1593_Static_assert(sizeof(struct nvme_firmware_page) == 512, "bad size for nvme_firmware_page");
1594
1595struct nvme_ns_list {
1596 uint32_t ns[1024];
1597} __packed __aligned(4);
1598
1599_Static_assert(sizeof(struct nvme_ns_list) == 4096, "bad size for nvme_ns_list");
1600
1601struct nvme_command_effects_page {
1602 uint32_t acs[256];
1603 uint32_t iocs[256];
1604 uint8_t reserved[2048];
1605} __packed __aligned(4);
1606
1607_Static_assert(sizeof(struct nvme_command_effects_page) == 4096,
1608 "bad size for nvme_command_effects_page");
1609
1610struct nvme_device_self_test_page {
1611 uint8_t curr_operation;
1612 uint8_t curr_compl;
1613 uint8_t rsvd2[2];
1614 struct {
1615 uint8_t status;
1616 uint8_t segment_num;
1617 uint8_t valid_diag_info;
1618 uint8_t rsvd3;
1619 uint64_t poh;
1620 uint32_t nsid;
1621 /* Define as an array to simplify alignment issues */
1622 uint8_t failing_lba[8];
1623 uint8_t status_code_type;
1624 uint8_t status_code;
1625 uint8_t vendor_specific[2];
1626 } __packed result[20];
1627} __packed __aligned(4);
1628
1629_Static_assert(sizeof(struct nvme_device_self_test_page) == 564,
1630 "bad size for nvme_device_self_test_page");
1631
1632struct nvme_discovery_log_entry {
1633 uint8_t trtype;
1634 uint8_t adrfam;
1635 uint8_t subtype;
1636 uint8_t treq;
1637 uint16_t portid;
1638 uint16_t cntlid;
1639 uint16_t aqsz;
1640 uint8_t reserved1[22];
1641 uint8_t trsvcid[32];
1642 uint8_t reserved2[192];
1643 uint8_t subnqn[256];
1644 uint8_t traddr[256];
1645 union {
1646 struct {
1647 uint8_t rdma_qptype;
1648 uint8_t rdma_prtype;
1649 uint8_t rdma_cms;
1650 uint8_t reserved[5];
1651 uint16_t rdma_pkey;
1652 } rdma;
1653 struct {
1654 uint8_t sectype;
1655 } tcp;
1656 uint8_t reserved[256];
1657 } tsas;
1658} __packed __aligned(4);
1659
1660_Static_assert(sizeof(struct nvme_discovery_log_entry) == 1024,
1661 "bad size for nvme_discovery_log_entry");
1662
1663struct nvme_discovery_log {
1664 uint64_t genctr;
1665 uint64_t numrec;
1666 uint16_t recfmt;
1667 uint8_t reserved[1006];
1668 struct nvme_discovery_log_entry entries[];
1669} __packed __aligned(4);
1670
1671_Static_assert(sizeof(struct nvme_discovery_log) == 1024,
1672 "bad size for nvme_discovery_log");
1673
1674struct nvme_res_notification_page {
1675 uint64_t log_page_count;
1676 uint8_t log_page_type;
1677 uint8_t available_log_pages;
1678 uint8_t reserved2;
1679 uint32_t nsid;
1680 uint8_t reserved[48];
1681} __packed __aligned(4);
1682
1683_Static_assert(sizeof(struct nvme_res_notification_page) == 64,
1684 "bad size for nvme_res_notification_page");
1685
1686struct nvme_sanitize_status_page {
1687 uint16_t sprog;
1688 uint16_t sstat;
1689 uint32_t scdw10;
1690 uint32_t etfo;
1691 uint32_t etfbe;
1692 uint32_t etfce;
1693 uint32_t etfownd;
1694 uint32_t etfbewnd;
1695 uint32_t etfcewnd;
1696 uint8_t reserved[480];
1697} __packed __aligned(4);
1698
1699_Static_assert(sizeof(struct nvme_sanitize_status_page) == 512,
1700 "bad size for nvme_sanitize_status_page");
1701
1702struct intel_log_temp_stats {
1703 uint64_t current;
1704 uint64_t overtemp_flag_last;
1705 uint64_t overtemp_flag_life;
1706 uint64_t max_temp;
1707 uint64_t min_temp;
1708 uint64_t _rsvd[5];
1709 uint64_t max_oper_temp;
1710 uint64_t min_oper_temp;
1711 uint64_t est_offset;
1712} __packed __aligned(4);
1713
1714_Static_assert(sizeof(struct intel_log_temp_stats) == 13 * 8, "bad size for intel_log_temp_stats");
1715
1716struct nvme_resv_reg_ctrlr {
1717 uint16_t ctrlr_id; /* Controller ID */
1718 uint8_t rcsts; /* Reservation Status */
1719 uint8_t reserved3[5];
1720 uint64_t hostid; /* Host Identifier */
1721 uint64_t rkey; /* Reservation Key */
1722} __packed __aligned(4);
1723
1724_Static_assert(sizeof(struct nvme_resv_reg_ctrlr) == 24, "bad size for nvme_resv_reg_ctrlr");
1725
1726struct nvme_resv_reg_ctrlr_ext {
1727 uint16_t ctrlr_id; /* Controller ID */
1728 uint8_t rcsts; /* Reservation Status */
1729 uint8_t reserved3[5];
1730 uint64_t rkey; /* Reservation Key */
1731 uint64_t hostid[2]; /* Host Identifier */
1732 uint8_t reserved32[32];
1733} __packed __aligned(4);
1734
1735_Static_assert(sizeof(struct nvme_resv_reg_ctrlr_ext) == 64, "bad size for nvme_resv_reg_ctrlr_ext");
1736
1737struct nvme_resv_status {
1738 uint32_t gen; /* Generation */
1739 uint8_t rtype; /* Reservation Type */
1740 uint8_t regctl[2]; /* Number of Registered Controllers */
1741 uint8_t reserved7[2];
1742 uint8_t ptpls; /* Persist Through Power Loss State */
1743 uint8_t reserved10[14];
1744 struct nvme_resv_reg_ctrlr ctrlr[0];
1745} __packed __aligned(4);
1746
1747_Static_assert(sizeof(struct nvme_resv_status) == 24, "bad size for nvme_resv_status");
1748
1749struct nvme_resv_status_ext {
1750 uint32_t gen; /* Generation */
1751 uint8_t rtype; /* Reservation Type */
1752 uint8_t regctl[2]; /* Number of Registered Controllers */
1753 uint8_t reserved7[2];
1754 uint8_t ptpls; /* Persist Through Power Loss State */
1755 uint8_t reserved10[14];
1756 uint8_t reserved24[40];
1757 struct nvme_resv_reg_ctrlr_ext ctrlr[0];
1758} __packed __aligned(4);
1759
1760_Static_assert(sizeof(struct nvme_resv_status_ext) == 64, "bad size for nvme_resv_status_ext");
1761
1762#define NVME_TEST_MAX_THREADS 128
1763
1764struct nvme_io_test {
1765 enum nvme_nvm_opcode opc;
1766 uint32_t size;
1767 uint32_t time; /* in seconds */
1768 uint32_t num_threads;
1769 uint32_t flags;
1770 uint64_t io_completed[NVME_TEST_MAX_THREADS];
1771};
1772
1773enum nvme_io_test_flags {
1774 /*
1775 * Specifies whether dev_refthread/dev_relthread should be
1776 * called during NVME_BIO_TEST. Ignored for other test
1777 * types.
1778 */
1779 NVME_TEST_FLAG_REFTHREAD = 0x1,
1780};
1781
1782struct nvme_pt_command {
1783 /*
1784 * cmd is used to specify a passthrough command to a controller or
1785 * namespace.
1786 *
1787 * The following fields from cmd may be specified by the caller:
1788 * * opc (opcode)
1789 * * nsid (namespace id) - for admin commands only
1790 * * cdw10-cdw15
1791 *
1792 * Remaining fields must be set to 0 by the caller.
1793 */
1794 struct nvme_command cmd;
1795
1796 /*
1797 * cpl returns completion status for the passthrough command
1798 * specified by cmd.
1799 *
1800 * The following fields will be filled out by the driver, for
1801 * consumption by the caller:
1802 * * cdw0
1803 * * status (except for phase)
1804 *
1805 * Remaining fields will be set to 0 by the driver.
1806 */
1807 struct nvme_completion cpl;
1808
1809 /* buf is the data buffer associated with this passthrough command. */
1810 void * buf;
1811
1812 /*
1813 * len is the length of the data buffer associated with this
1814 * passthrough command.
1815 */
1816 uint32_t len;
1817
1818 /*
1819 * is_read = 1 if the passthrough command will read data into the
1820 * supplied buffer from the controller.
1821 *
1822 * is_read = 0 if the passthrough command will write data from the
1823 * supplied buffer to the controller.
1824 */
1825 uint32_t is_read;
1826
1827 /*
1828 * driver_lock is used by the driver only. It must be set to 0
1829 * by the caller.
1830 */
1831 struct mtx * driver_lock;
1832};
1833
1834struct nvme_get_nsid {
1835 char cdev[SPECNAMELEN + 1];
1836 uint32_t nsid;
1837};
1838
1839struct nvme_hmb_desc {
1840 uint64_t addr;
1841 uint32_t size;
1842 uint32_t reserved;
1843};
1844
1845#define nvme_completion_is_error(cpl) \
1846 (NVME_STATUS_GET_SC((cpl)->status) != 0 || NVME_STATUS_GET_SCT((cpl)->status) != 0)
1847
1848void nvme_strvis(uint8_t *dst, const uint8_t *src, int dstlen, int srclen);
1849
1850#ifdef _KERNEL
1851
1852struct bio;
1853struct thread;
1854
1855struct nvme_namespace;
1856struct nvme_controller;
1857struct nvme_consumer;
1858
1859typedef void (*nvme_cb_fn_t)(void *, const struct nvme_completion *);
1860
1861typedef void *(*nvme_cons_ns_fn_t)(struct nvme_namespace *, void *);
1862typedef void *(*nvme_cons_ctrlr_fn_t)(struct nvme_controller *);
1863typedef void (*nvme_cons_async_fn_t)(void *, const struct nvme_completion *,
1864 uint32_t, void *, uint32_t);
1865typedef void (*nvme_cons_fail_fn_t)(void *);
1866
1867enum nvme_namespace_flags {
1868 NVME_NS_DEALLOCATE_SUPPORTED = 0x1,
1869 NVME_NS_FLUSH_SUPPORTED = 0x2,
1870};
1871
1872int nvme_ctrlr_passthrough_cmd(struct nvme_controller *ctrlr,
1873 struct nvme_pt_command *pt,
1874 uint32_t nsid, int is_user_buffer,
1875 int is_admin_cmd);
1876
1877/* Admin functions */
1878void nvme_ctrlr_cmd_set_feature(struct nvme_controller *ctrlr,
1879 uint8_t feature, uint32_t cdw11,
1880 uint32_t cdw12, uint32_t cdw13,
1881 uint32_t cdw14, uint32_t cdw15,
1882 void *payload, uint32_t payload_size,
1883 nvme_cb_fn_t cb_fn, void *cb_arg);
1884void nvme_ctrlr_cmd_get_feature(struct nvme_controller *ctrlr,
1885 uint8_t feature, uint32_t cdw11,
1886 void *payload, uint32_t payload_size,
1887 nvme_cb_fn_t cb_fn, void *cb_arg);
1888void nvme_ctrlr_cmd_get_log_page(struct nvme_controller *ctrlr,
1889 uint8_t log_page, uint32_t nsid,
1890 void *payload, uint32_t payload_size,
1891 nvme_cb_fn_t cb_fn, void *cb_arg);
1892
1893/* NVM I/O functions */
1894int nvme_ns_cmd_write(struct nvme_namespace *ns, void *payload,
1895 uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn,
1896 void *cb_arg);
1897int nvme_ns_cmd_write_bio(struct nvme_namespace *ns, struct bio *bp,
1898 nvme_cb_fn_t cb_fn, void *cb_arg);
1899int nvme_ns_cmd_read(struct nvme_namespace *ns, void *payload,
1900 uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn,
1901 void *cb_arg);
1902int nvme_ns_cmd_read_bio(struct nvme_namespace *ns, struct bio *bp,
1903 nvme_cb_fn_t cb_fn, void *cb_arg);
1904int nvme_ns_cmd_deallocate(struct nvme_namespace *ns, void *payload,
1905 uint8_t num_ranges, nvme_cb_fn_t cb_fn,
1906 void *cb_arg);
1907int nvme_ns_cmd_flush(struct nvme_namespace *ns, nvme_cb_fn_t cb_fn,
1908 void *cb_arg);
1909int nvme_ns_dump(struct nvme_namespace *ns, void *virt, off_t offset,
1910 size_t len);
1911
1912/* Registration functions */
1913struct nvme_consumer * nvme_register_consumer(nvme_cons_ns_fn_t ns_fn,
1914 nvme_cons_ctrlr_fn_t ctrlr_fn,
1915 nvme_cons_async_fn_t async_fn,
1916 nvme_cons_fail_fn_t fail_fn);
1917void nvme_unregister_consumer(struct nvme_consumer *consumer);
1918
1919/* Controller helper functions */
1920device_t nvme_ctrlr_get_device(struct nvme_controller *ctrlr);
1921const struct nvme_controller_data *
1922 nvme_ctrlr_get_data(struct nvme_controller *ctrlr);
1923static inline bool
1924nvme_ctrlr_has_dataset_mgmt(const struct nvme_controller_data *cd)
1925{
1926 /* Assumes cd was byte swapped by nvme_controller_data_swapbytes() */
1927 return (NVMEV(NVME_CTRLR_DATA_ONCS_DSM, cd->oncs) != 0);
1928}
1929
1930/* Namespace helper functions */
1931uint32_t nvme_ns_get_max_io_xfer_size(struct nvme_namespace *ns);
1932uint32_t nvme_ns_get_sector_size(struct nvme_namespace *ns);
1933uint64_t nvme_ns_get_num_sectors(struct nvme_namespace *ns);
1934uint64_t nvme_ns_get_size(struct nvme_namespace *ns);
1935uint32_t nvme_ns_get_flags(struct nvme_namespace *ns);
1936const char * nvme_ns_get_serial_number(struct nvme_namespace *ns);
1937const char * nvme_ns_get_model_number(struct nvme_namespace *ns);
1938const struct nvme_namespace_data *
1939 nvme_ns_get_data(struct nvme_namespace *ns);
1940uint32_t nvme_ns_get_stripesize(struct nvme_namespace *ns);
1941
1942int nvme_ns_bio_process(struct nvme_namespace *ns, struct bio *bp,
1943 nvme_cb_fn_t cb_fn);
1944int nvme_ns_ioctl_process(struct nvme_namespace *ns, u_long cmd,
1945 caddr_t arg, int flag, struct thread *td);
1946
1947/*
1948 * Command building helper functions -- shared with CAM
1949 * These functions assume allocator zeros out cmd structure
1950 * CAM's xpt_get_ccb and the request allocator for nvme both
1951 * do zero'd allocations.
1952 */
1953static inline
1954void nvme_ns_flush_cmd(struct nvme_command *cmd, uint32_t nsid)
1955{
1956
1957 cmd->opc = NVME_OPC_FLUSH;
1958 cmd->nsid = htole32(nsid);
1959}
1960
1961static inline
1962void nvme_ns_rw_cmd(struct nvme_command *cmd, uint32_t rwcmd, uint32_t nsid,
1963 uint64_t lba, uint32_t count)
1964{
1965 cmd->opc = rwcmd;
1966 cmd->nsid = htole32(nsid);
1967 cmd->cdw10 = htole32(lba & 0xffffffffu);
1968 cmd->cdw11 = htole32(lba >> 32);
1969 cmd->cdw12 = htole32(count-1);
1970}
1971
1972static inline
1973void nvme_ns_write_cmd(struct nvme_command *cmd, uint32_t nsid,
1974 uint64_t lba, uint32_t count)
1975{
1976 nvme_ns_rw_cmd(cmd, NVME_OPC_WRITE, nsid, lba, count);
1977}
1978
1979static inline
1980void nvme_ns_read_cmd(struct nvme_command *cmd, uint32_t nsid,
1981 uint64_t lba, uint32_t count)
1982{
1983 nvme_ns_rw_cmd(cmd, NVME_OPC_READ, nsid, lba, count);
1984}
1985
1986static inline
1987void nvme_ns_trim_cmd(struct nvme_command *cmd, uint32_t nsid,
1988 uint32_t num_ranges)
1989{
1990 cmd->opc = NVME_OPC_DATASET_MANAGEMENT;
1991 cmd->nsid = htole32(nsid);
1992 cmd->cdw10 = htole32(num_ranges - 1);
1993 cmd->cdw11 = htole32(NVME_DSM_ATTR_DEALLOCATE);
1994}
1995
1996extern int nvme_use_nvd;
1997
1998#endif /* _KERNEL */
1999
2000/* Endianess conversion functions for NVMe structs */
2001static inline
2002void nvme_completion_swapbytes(struct nvme_completion *s __unused)
2003{
2004#if _BYTE_ORDER != _LITTLE_ENDIAN
2005
2006 s->cdw0 = le32toh(s->cdw0);
2007 /* omit rsvd1 */
2008 s->sqhd = le16toh(s->sqhd);
2009 s->sqid = le16toh(s->sqid);
2010 /* omit cid */
2011 s->status = le16toh(s->status);
2012#endif
2013}
2014
2015static inline
2016void nvme_power_state_swapbytes(struct nvme_power_state *s __unused)
2017{
2018#if _BYTE_ORDER != _LITTLE_ENDIAN
2019
2020 s->mp = le16toh(s->mp);
2021 s->enlat = le32toh(s->enlat);
2022 s->exlat = le32toh(s->exlat);
2023 s->idlp = le16toh(s->idlp);
2024 s->actp = le16toh(s->actp);
2025#endif
2026}
2027
2028static inline
2029void nvme_controller_data_swapbytes(struct nvme_controller_data *s __unused)
2030{
2031#if _BYTE_ORDER != _LITTLE_ENDIAN
2032 int i;
2033
2034 s->vid = le16toh(s->vid);
2035 s->ssvid = le16toh(s->ssvid);
2036 s->ctrlr_id = le16toh(s->ctrlr_id);
2037 s->ver = le32toh(s->ver);
2038 s->rtd3r = le32toh(s->rtd3r);
2039 s->rtd3e = le32toh(s->rtd3e);
2040 s->oaes = le32toh(s->oaes);
2041 s->ctratt = le32toh(s->ctratt);
2042 s->rrls = le16toh(s->rrls);
2043 s->crdt1 = le16toh(s->crdt1);
2044 s->crdt2 = le16toh(s->crdt2);
2045 s->crdt3 = le16toh(s->crdt3);
2046 s->oacs = le16toh(s->oacs);
2047 s->wctemp = le16toh(s->wctemp);
2048 s->cctemp = le16toh(s->cctemp);
2049 s->mtfa = le16toh(s->mtfa);
2050 s->hmpre = le32toh(s->hmpre);
2051 s->hmmin = le32toh(s->hmmin);
2052 s->rpmbs = le32toh(s->rpmbs);
2053 s->edstt = le16toh(s->edstt);
2054 s->kas = le16toh(s->kas);
2055 s->hctma = le16toh(s->hctma);
2056 s->mntmt = le16toh(s->mntmt);
2057 s->mxtmt = le16toh(s->mxtmt);
2058 s->sanicap = le32toh(s->sanicap);
2059 s->hmminds = le32toh(s->hmminds);
2060 s->hmmaxd = le16toh(s->hmmaxd);
2061 s->nsetidmax = le16toh(s->nsetidmax);
2062 s->endgidmax = le16toh(s->endgidmax);
2063 s->anagrpmax = le32toh(s->anagrpmax);
2064 s->nanagrpid = le32toh(s->nanagrpid);
2065 s->pels = le32toh(s->pels);
2066 s->maxcmd = le16toh(s->maxcmd);
2067 s->nn = le32toh(s->nn);
2068 s->oncs = le16toh(s->oncs);
2069 s->fuses = le16toh(s->fuses);
2070 s->awun = le16toh(s->awun);
2071 s->awupf = le16toh(s->awupf);
2072 s->acwu = le16toh(s->acwu);
2073 s->sgls = le32toh(s->sgls);
2074 s->mnan = le32toh(s->mnan);
2075 s->ioccsz = le32toh(s->ioccsz);
2076 s->iorcsz = le32toh(s->iorcsz);
2077 s->icdoff = le16toh(s->icdoff);
2078 s->ofcs = le16toh(s->ofcs);
2079 for (i = 0; i < 32; i++)
2080 nvme_power_state_swapbytes(&s->power_state[i]);
2081#endif
2082}
2083
2084static inline
2085void nvme_namespace_data_swapbytes(struct nvme_namespace_data *s __unused)
2086{
2087#if _BYTE_ORDER != _LITTLE_ENDIAN
2088 int i;
2089
2090 s->nsze = le64toh(s->nsze);
2091 s->ncap = le64toh(s->ncap);
2092 s->nuse = le64toh(s->nuse);
2093 s->nawun = le16toh(s->nawun);
2094 s->nawupf = le16toh(s->nawupf);
2095 s->nacwu = le16toh(s->nacwu);
2096 s->nabsn = le16toh(s->nabsn);
2097 s->nabo = le16toh(s->nabo);
2098 s->nabspf = le16toh(s->nabspf);
2099 s->noiob = le16toh(s->noiob);
2100 s->npwg = le16toh(s->npwg);
2101 s->npwa = le16toh(s->npwa);
2102 s->npdg = le16toh(s->npdg);
2103 s->npda = le16toh(s->npda);
2104 s->nows = le16toh(s->nows);
2105 s->anagrpid = le32toh(s->anagrpid);
2106 s->nvmsetid = le16toh(s->nvmsetid);
2107 s->endgid = le16toh(s->endgid);
2108 for (i = 0; i < 16; i++)
2109 s->lbaf[i] = le32toh(s->lbaf[i]);
2110#endif
2111}
2112
2113static inline
2114void nvme_error_information_entry_swapbytes(
2115 struct nvme_error_information_entry *s __unused)
2116{
2117#if _BYTE_ORDER != _LITTLE_ENDIAN
2118
2119 s->error_count = le64toh(s->error_count);
2120 s->sqid = le16toh(s->sqid);
2121 s->cid = le16toh(s->cid);
2122 s->status = le16toh(s->status);
2123 s->error_location = le16toh(s->error_location);
2124 s->lba = le64toh(s->lba);
2125 s->nsid = le32toh(s->nsid);
2126 s->csi = le64toh(s->csi);
2127 s->ttsi = le16toh(s->ttsi);
2128#endif
2129}
2130
2131static inline
2132void nvme_le128toh(void *p __unused)
2133{
2134#if _BYTE_ORDER != _LITTLE_ENDIAN
2135 /* Swap 16 bytes in place */
2136 char *tmp = (char*)p;
2137 char b;
2138 int i;
2139 for (i = 0; i < 8; i++) {
2140 b = tmp[i];
2141 tmp[i] = tmp[15-i];
2142 tmp[15-i] = b;
2143 }
2144#endif
2145}
2146
2147static inline
2148void nvme_health_information_page_swapbytes(
2149 struct nvme_health_information_page *s __unused)
2150{
2151#if _BYTE_ORDER != _LITTLE_ENDIAN
2152 int i;
2153
2154 s->temperature = le16toh(s->temperature);
2155 nvme_le128toh((void *)s->data_units_read);
2156 nvme_le128toh((void *)s->data_units_written);
2157 nvme_le128toh((void *)s->host_read_commands);
2158 nvme_le128toh((void *)s->host_write_commands);
2159 nvme_le128toh((void *)s->controller_busy_time);
2160 nvme_le128toh((void *)s->power_cycles);
2161 nvme_le128toh((void *)s->power_on_hours);
2162 nvme_le128toh((void *)s->unsafe_shutdowns);
2163 nvme_le128toh((void *)s->media_errors);
2164 nvme_le128toh((void *)s->num_error_info_log_entries);
2165 s->warning_temp_time = le32toh(s->warning_temp_time);
2166 s->error_temp_time = le32toh(s->error_temp_time);
2167 for (i = 0; i < 8; i++)
2168 s->temp_sensor[i] = le16toh(s->temp_sensor[i]);
2169 s->tmt1tc = le32toh(s->tmt1tc);
2170 s->tmt2tc = le32toh(s->tmt2tc);
2171 s->ttftmt1 = le32toh(s->ttftmt1);
2172 s->ttftmt2 = le32toh(s->ttftmt2);
2173#endif
2174}
2175
2176static inline
2177void nvme_ns_list_swapbytes(struct nvme_ns_list *s __unused)
2178{
2179#if _BYTE_ORDER != _LITTLE_ENDIAN
2180 int i;
2181
2182 for (i = 0; i < 1024; i++)
2183 s->ns[i] = le32toh(s->ns[i]);
2184#endif
2185}
2186
2187static inline
2188void nvme_command_effects_page_swapbytes(
2189 struct nvme_command_effects_page *s __unused)
2190{
2191#if _BYTE_ORDER != _LITTLE_ENDIAN
2192 int i;
2193
2194 for (i = 0; i < 256; i++)
2195 s->acs[i] = le32toh(s->acs[i]);
2196 for (i = 0; i < 256; i++)
2197 s->iocs[i] = le32toh(s->iocs[i]);
2198#endif
2199}
2200
2201static inline
2202void nvme_res_notification_page_swapbytes(
2203 struct nvme_res_notification_page *s __unused)
2204{
2205#if _BYTE_ORDER != _LITTLE_ENDIAN
2206 s->log_page_count = le64toh(s->log_page_count);
2207 s->nsid = le32toh(s->nsid);
2208#endif
2209}
2210
2211static inline
2212void nvme_sanitize_status_page_swapbytes(
2213 struct nvme_sanitize_status_page *s __unused)
2214{
2215#if _BYTE_ORDER != _LITTLE_ENDIAN
2216 s->sprog = le16toh(s->sprog);
2217 s->sstat = le16toh(s->sstat);
2218 s->scdw10 = le32toh(s->scdw10);
2219 s->etfo = le32toh(s->etfo);
2220 s->etfbe = le32toh(s->etfbe);
2221 s->etfce = le32toh(s->etfce);
2222 s->etfownd = le32toh(s->etfownd);
2223 s->etfbewnd = le32toh(s->etfbewnd);
2224 s->etfcewnd = le32toh(s->etfcewnd);
2225#endif
2226}
2227
2228static inline
2229void nvme_resv_status_swapbytes(struct nvme_resv_status *s __unused,
2230 size_t size __unused)
2231{
2232#if _BYTE_ORDER != _LITTLE_ENDIAN
2233 size_t i, n;
2234
2235 s->gen = le32toh(s->gen);
2236 n = (s->regctl[1] << 8) | s->regctl[0];
2237 n = MIN(n, (size - sizeof(s)) / sizeof(s->ctrlr[0]));
2238 for (i = 0; i < n; i++) {
2239 s->ctrlr[i].ctrlr_id = le16toh(s->ctrlr[i].ctrlr_id);
2240 s->ctrlr[i].hostid = le64toh(s->ctrlr[i].hostid);
2241 s->ctrlr[i].rkey = le64toh(s->ctrlr[i].rkey);
2242 }
2243#endif
2244}
2245
2246static inline
2247void nvme_resv_status_ext_swapbytes(struct nvme_resv_status_ext *s __unused,
2248 size_t size __unused)
2249{
2250#if _BYTE_ORDER != _LITTLE_ENDIAN
2251 size_t i, n;
2252
2253 s->gen = le32toh(s->gen);
2254 n = (s->regctl[1] << 8) | s->regctl[0];
2255 n = MIN(n, (size - sizeof(s)) / sizeof(s->ctrlr[0]));
2256 for (i = 0; i < n; i++) {
2257 s->ctrlr[i].ctrlr_id = le16toh(s->ctrlr[i].ctrlr_id);
2258 s->ctrlr[i].rkey = le64toh(s->ctrlr[i].rkey);
2259 nvme_le128toh((void *)s->ctrlr[i].hostid);
2260 }
2261#endif
2262}
2263
2264static inline void
2265nvme_device_self_test_swapbytes(struct nvme_device_self_test_page *s __unused)
2266{
2267#if _BYTE_ORDER != _LITTLE_ENDIAN
2268 uint8_t *tmp;
2269 uint32_t r, i;
2270 uint8_t b;
2271
2272 for (r = 0; r < 20; r++) {
2273 s->result[r].poh = le64toh(s->result[r].poh);
2274 s->result[r].nsid = le32toh(s->result[r].nsid);
2275 /* Unaligned 64-bit loads fail on some architectures */
2276 tmp = s->result[r].failing_lba;
2277 for (i = 0; i < 4; i++) {
2278 b = tmp[i];
2279 tmp[i] = tmp[7-i];
2280 tmp[7-i] = b;
2281 }
2282 }
2283#endif
2284}
2285
2286static inline void
2287nvme_discovery_log_entry_swapbytes(struct nvme_discovery_log_entry *s __unused)
2288{
2289#if _BYTE_ORDER != _LITTLE_ENDIAN
2290 s->portid = le16toh(s->portid);
2291 s->cntlid = le16toh(s->cntlid);
2292 s->aqsz = le16toh(s->aqsz);
2293 if (s->trtype == 0x01 /* RDMA */) {
2294 s->tsas.rdma.rdma_pkey = le16toh(s->tsas.rdma.rdma_pkey);
2295 }
2296#endif
2297}
2298
2299static inline void
2300nvme_discovery_log_swapbytes(struct nvme_discovery_log *s __unused)
2301{
2302#if _BYTE_ORDER != _LITTLE_ENDIAN
2303 s->genctr = le64toh(s->genctr);
2304 s->numrec = le64toh(s->numrec);
2305 s->recfmt = le16toh(s->recfmt);
2306#endif
2307}
2308#endif /* __NVME_H__ */