master
1/*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2006 M. Warner Losh <imp@FreeBSD.org>
5 * Copyright (c) 2017 Marius Strobl <marius@FreeBSD.org>
6 * Copyright (c) 2015-2016 Ilya Bakulin <kibab@FreeBSD.org>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Portions of this software may have been developed with reference to
29 * the SD Simplified Specification. The following disclaimer may apply:
30 *
31 * The following conditions apply to the release of the simplified
32 * specification ("Simplified Specification") by the SD Card Association and
33 * the SD Group. The Simplified Specification is a subset of the complete SD
34 * Specification which is owned by the SD Card Association and the SD
35 * Group. This Simplified Specification is provided on a non-confidential
36 * basis subject to the disclaimers below. Any implementation of the
37 * Simplified Specification may require a license from the SD Card
38 * Association, SD Group, SD-3C LLC or other third parties.
39 *
40 * Disclaimers:
41 *
42 * The information contained in the Simplified Specification is presented only
43 * as a standard specification for SD Cards and SD Host/Ancillary products and
44 * is provided "AS-IS" without any representations or warranties of any
45 * kind. No responsibility is assumed by the SD Group, SD-3C LLC or the SD
46 * Card Association for any damages, any infringements of patents or other
47 * right of the SD Group, SD-3C LLC, the SD Card Association or any third
48 * parties, which may result from its use. No license is granted by
49 * implication, estoppel or otherwise under any patent or other rights of the
50 * SD Group, SD-3C LLC, the SD Card Association or any third party. Nothing
51 * herein shall be construed as an obligation by the SD Group, the SD-3C LLC
52 * or the SD Card Association to disclose or distribute any technical
53 * information, know-how or other confidential information to any third party.
54 */
55
56#ifndef DEV_MMC_MMCREG_H
57#define DEV_MMC_MMCREG_H
58
59/*
60 * This file contains the register definitions for the mmc and sd buses.
61 * They are taken from publicly available sources.
62 */
63
64struct mmc_data;
65struct mmc_request;
66
67struct mmc_command {
68 uint32_t opcode;
69 uint32_t arg;
70 uint32_t resp[4];
71 uint32_t flags; /* Expected responses */
72#define MMC_RSP_PRESENT (1ul << 0) /* Response */
73#define MMC_RSP_136 (1ul << 1) /* 136 bit response */
74#define MMC_RSP_CRC (1ul << 2) /* Expect valid crc */
75#define MMC_RSP_BUSY (1ul << 3) /* Card may send busy */
76#define MMC_RSP_OPCODE (1ul << 4) /* Response include opcode */
77#define MMC_RSP_MASK 0x1ful
78#define MMC_CMD_AC (0ul << 5) /* Addressed Command, no data */
79#define MMC_CMD_ADTC (1ul << 5) /* Addressed Data transfer cmd */
80#define MMC_CMD_BC (2ul << 5) /* Broadcast command, no response */
81#define MMC_CMD_BCR (3ul << 5) /* Broadcast command with response */
82#define MMC_CMD_MASK (3ul << 5)
83
84/* Possible response types defined in the standard: */
85#define MMC_RSP_NONE (0)
86#define MMC_RSP_R1 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
87#define MMC_RSP_R1B (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE | MMC_RSP_BUSY)
88#define MMC_RSP_R2 (MMC_RSP_PRESENT | MMC_RSP_136 | MMC_RSP_CRC)
89#define MMC_RSP_R3 (MMC_RSP_PRESENT)
90#define MMC_RSP_R4 (MMC_RSP_PRESENT)
91#define MMC_RSP_R5 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
92#define MMC_RSP_R5B (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE | MMC_RSP_BUSY)
93#define MMC_RSP_R6 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
94#define MMC_RSP_R7 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
95#define MMC_RSP(x) ((x) & MMC_RSP_MASK)
96 uint32_t retries;
97 uint32_t error;
98#define MMC_ERR_NONE 0
99#define MMC_ERR_TIMEOUT 1
100#define MMC_ERR_BADCRC 2
101#define MMC_ERR_FIFO 3
102#define MMC_ERR_FAILED 4
103#define MMC_ERR_INVALID 5
104#define MMC_ERR_NO_MEMORY 6
105#define MMC_ERR_MAX 6
106 struct mmc_data *data; /* Data segment with cmd */
107 struct mmc_request *mrq; /* backpointer to request */
108};
109
110/*
111 * R1 responses
112 *
113 * Types (per SD 2.0 standard)
114 * e : error bit
115 * s : status bit
116 * r : detected and set for the actual command response
117 * x : Detected and set during command execution. The host can get
118 * the status by issuing a command with R1 response.
119 *
120 * Clear Condition (per SD 2.0 standard)
121 * a : according to the card current state.
122 * b : always related to the previous command. reception of a valid
123 * command will clear it (with a delay of one command).
124 * c : clear by read
125 */
126#define R1_OUT_OF_RANGE (1u << 31) /* erx, c */
127#define R1_ADDRESS_ERROR (1u << 30) /* erx, c */
128#define R1_BLOCK_LEN_ERROR (1u << 29) /* erx, c */
129#define R1_ERASE_SEQ_ERROR (1u << 28) /* er, c */
130#define R1_ERASE_PARAM (1u << 27) /* erx, c */
131#define R1_WP_VIOLATION (1u << 26) /* erx, c */
132#define R1_CARD_IS_LOCKED (1u << 25) /* sx, a */
133#define R1_LOCK_UNLOCK_FAILED (1u << 24) /* erx, c */
134#define R1_COM_CRC_ERROR (1u << 23) /* er, b */
135#define R1_ILLEGAL_COMMAND (1u << 22) /* er, b */
136#define R1_CARD_ECC_FAILED (1u << 21) /* erx, c */
137#define R1_CC_ERROR (1u << 20) /* erx, c */
138#define R1_ERROR (1u << 19) /* erx, c */
139#define R1_CSD_OVERWRITE (1u << 16) /* erx, c */
140#define R1_WP_ERASE_SKIP (1u << 15) /* erx, c */
141#define R1_CARD_ECC_DISABLED (1u << 14) /* sx, a */
142#define R1_ERASE_RESET (1u << 13) /* sr, c */
143#define R1_CURRENT_STATE_MASK (0xfu << 9) /* sx, b */
144#define R1_READY_FOR_DATA (1u << 8) /* sx, a */
145#define R1_SWITCH_ERROR (1u << 7) /* sx, c */
146#define R1_APP_CMD (1u << 5) /* sr, c */
147#define R1_AKE_SEQ_ERROR (1u << 3) /* er, c */
148#define R1_STATUS(x) ((x) & 0xFFFFE000)
149#define R1_CURRENT_STATE(x) (((x) & R1_CURRENT_STATE_MASK) >> 9)
150#define R1_STATE_IDLE 0
151#define R1_STATE_READY 1
152#define R1_STATE_IDENT 2
153#define R1_STATE_STBY 3
154#define R1_STATE_TRAN 4
155#define R1_STATE_DATA 5
156#define R1_STATE_RCV 6
157#define R1_STATE_PRG 7
158#define R1_STATE_DIS 8
159
160/* R4 responses (SDIO) */
161#define R4_IO_NUM_FUNCTIONS(ocr) (((ocr) >> 28) & 0x3)
162#define R4_IO_MEM_PRESENT (0x1 << 27)
163#define R4_IO_OCR_MASK 0x00fffff0
164
165/*
166 * R5 responses
167 *
168 * Types (per SD 2.0 standard)
169 * e : error bit
170 * s : status bit
171 * r : detected and set for the actual command response
172 * x : Detected and set during command execution. The host can get
173 * the status by issuing a command with R1 response.
174 *
175 * Clear Condition (per SD 2.0 standard)
176 * a : according to the card current state.
177 * b : always related to the previous command. reception of a valid
178 * command will clear it (with a delay of one command).
179 * c : clear by read
180 */
181#define R5_COM_CRC_ERROR (1u << 15) /* er, b */
182#define R5_ILLEGAL_COMMAND (1u << 14) /* er, b */
183#define R5_IO_CURRENT_STATE_MASK (3u << 12) /* s, b */
184#define R5_IO_CURRENT_STATE(x) (((x) & R5_IO_CURRENT_STATE_MASK) >> 12)
185#define R5_ERROR (1u << 11) /* erx, c */
186#define R5_FUNCTION_NUMBER (1u << 9) /* er, c */
187#define R5_OUT_OF_RANGE (1u << 8) /* er, c */
188
189struct mmc_data {
190 size_t len; /* size of the data */
191 size_t xfer_len;
192 void *data; /* data buffer */
193 uint32_t flags;
194#define MMC_DATA_WRITE (1UL << 0)
195#define MMC_DATA_READ (1UL << 1)
196#define MMC_DATA_STREAM (1UL << 2)
197#define MMC_DATA_MULTI (1UL << 3)
198#define MMC_DATA_BLOCK_SIZE (1UL << 4)
199 struct mmc_request *mrq;
200 size_t block_size; /* block size for CMD53 */
201 size_t block_count; /* block count for CMD53 */
202};
203
204struct mmc_request {
205 struct mmc_command *cmd;
206 struct mmc_command *stop;
207 void (*done)(struct mmc_request *); /* Completion function */
208 void *done_data; /* requestor set data */
209 uint32_t flags;
210#define MMC_REQ_DONE 1
211#define MMC_TUNE_DONE 2
212};
213
214/* Command definitions */
215
216/* Class 0 and 1: Basic commands & read stream commands */
217#define MMC_GO_IDLE_STATE 0
218#define MMC_SEND_OP_COND 1
219#define MMC_ALL_SEND_CID 2
220#define MMC_SET_RELATIVE_ADDR 3
221#define SD_SEND_RELATIVE_ADDR 3
222#define MMC_SET_DSR 4
223#define MMC_SLEEP_AWAKE 5
224#define IO_SEND_OP_COND 5
225#define MMC_SWITCH_FUNC 6
226#define MMC_SWITCH_FUNC_CMDS 0
227#define MMC_SWITCH_FUNC_SET 1
228#define MMC_SWITCH_FUNC_CLR 2
229#define MMC_SWITCH_FUNC_WR 3
230#define MMC_SELECT_CARD 7
231#define MMC_DESELECT_CARD 7
232#define MMC_SEND_EXT_CSD 8
233#define SD_SEND_IF_COND 8
234#define MMC_SEND_CSD 9
235#define MMC_SEND_CID 10
236#define MMC_READ_DAT_UNTIL_STOP 11
237#define MMC_STOP_TRANSMISSION 12
238#define MMC_SEND_STATUS 13
239#define MMC_BUSTEST_R 14
240#define MMC_GO_INACTIVE_STATE 15
241#define MMC_BUSTEST_W 19
242
243/* Class 2: Block oriented read commands */
244#define MMC_SET_BLOCKLEN 16
245#define MMC_READ_SINGLE_BLOCK 17
246#define MMC_READ_MULTIPLE_BLOCK 18
247#define MMC_SEND_TUNING_BLOCK 19
248#define MMC_SEND_TUNING_BLOCK_HS200 21
249
250/* Class 3: Stream write commands */
251#define MMC_WRITE_DAT_UNTIL_STOP 20
252 /* reserved: 22 */
253
254/* Class 4: Block oriented write commands */
255#define MMC_SET_BLOCK_COUNT 23
256#define MMC_WRITE_BLOCK 24
257#define MMC_WRITE_MULTIPLE_BLOCK 25
258#define MMC_PROGARM_CID 26
259#define MMC_PROGRAM_CSD 27
260
261/* Class 6: Block oriented write protection commands */
262#define MMC_SET_WRITE_PROT 28
263#define MMC_CLR_WRITE_PROT 29
264#define MMC_SEND_WRITE_PROT 30
265 /* reserved: 31 */
266
267/* Class 5: Erase commands */
268#define SD_ERASE_WR_BLK_START 32
269#define SD_ERASE_WR_BLK_END 33
270 /* 34 -- reserved old command */
271#define MMC_ERASE_GROUP_START 35
272#define MMC_ERASE_GROUP_END 36
273 /* 37 -- reserved old command */
274#define MMC_ERASE 38
275#define MMC_ERASE_ERASE 0x00000000
276#define MMC_ERASE_TRIM 0x00000001
277#define MMC_ERASE_FULE 0x00000002
278#define MMC_ERASE_DISCARD 0x00000003
279#define MMC_ERASE_SECURE_ERASE 0x80000000
280#define MMC_ERASE_SECURE_TRIM1 0x80000001
281#define MMC_ERASE_SECURE_TRIM2 0x80008000
282
283/* Class 9: I/O mode commands */
284#define MMC_FAST_IO 39
285#define MMC_GO_IRQ_STATE 40
286 /* reserved: 41 */
287
288/* Class 7: Lock card */
289#define MMC_LOCK_UNLOCK 42
290 /* reserved: 43 */
291 /* reserved: 44 */
292 /* reserved: 45 */
293 /* reserved: 46 */
294 /* reserved: 47 */
295 /* reserved: 48 */
296 /* reserved: 49 */
297 /* reserved: 50 */
298 /* reserved: 51 */
299 /* reserved: 54 */
300
301/* Class 8: Application specific commands */
302#define MMC_APP_CMD 55
303#define MMC_GEN_CMD 56
304 /* reserved: 57 */
305 /* reserved: 58 */
306 /* reserved: 59 */
307 /* reserved for mfg: 60 */
308 /* reserved for mfg: 61 */
309 /* reserved for mfg: 62 */
310 /* reserved for mfg: 63 */
311
312/* Class 9: I/O cards (sd) */
313#define SD_IO_RW_DIRECT 52
314/* CMD52 arguments */
315#define SD_ARG_CMD52_READ (0 << 31)
316#define SD_ARG_CMD52_WRITE (1 << 31)
317#define SD_ARG_CMD52_FUNC_SHIFT 28
318#define SD_ARG_CMD52_FUNC_MASK 0x7
319#define SD_ARG_CMD52_EXCHANGE (1 << 27)
320#define SD_ARG_CMD52_REG_SHIFT 9
321#define SD_ARG_CMD52_REG_MASK 0x1ffff
322#define SD_ARG_CMD52_DATA_SHIFT 0
323#define SD_ARG_CMD52_DATA_MASK 0xff
324#define SD_R5_DATA(resp) ((resp)[0] & 0xff)
325
326#define SD_IO_RW_EXTENDED 53
327/* CMD53 arguments */
328#define SD_ARG_CMD53_READ (0 << 31)
329#define SD_ARG_CMD53_WRITE (1 << 31)
330#define SD_ARG_CMD53_FUNC_SHIFT 28
331#define SD_ARG_CMD53_FUNC_MASK 0x7
332#define SD_ARG_CMD53_BLOCK_MODE (1 << 27)
333#define SD_ARG_CMD53_INCREMENT (1 << 26)
334#define SD_ARG_CMD53_REG_SHIFT 9
335#define SD_ARG_CMD53_REG_MASK 0x1ffff
336#define SD_ARG_CMD53_LENGTH_SHIFT 0
337#define SD_ARG_CMD53_LENGTH_MASK 0x1ff
338#define SD_ARG_CMD53_LENGTH_MAX 64 /* XXX should be 511? */
339
340/* Class 10: Switch function commands */
341#define SD_SWITCH_FUNC 6
342 /* reserved: 34 */
343 /* reserved: 35 */
344 /* reserved: 36 */
345 /* reserved: 37 */
346 /* reserved: 50 */
347 /* reserved: 57 */
348
349/* Application specific commands for SD */
350#define ACMD_SET_BUS_WIDTH 6
351#define ACMD_SD_STATUS 13
352#define ACMD_SEND_NUM_WR_BLOCKS 22
353#define ACMD_SET_WR_BLK_ERASE_COUNT 23
354#define ACMD_SD_SEND_OP_COND 41
355#define ACMD_SET_CLR_CARD_DETECT 42
356#define ACMD_SEND_SCR 51
357
358/*
359 * EXT_CSD fields
360 */
361#define EXT_CSD_FLUSH_CACHE 32 /* W/E */
362#define EXT_CSD_CACHE_CTRL 33 /* R/W/E */
363#define EXT_CSD_EXT_PART_ATTR 52 /* R/W, 2 bytes */
364#define EXT_CSD_ENH_START_ADDR 136 /* R/W, 4 bytes */
365#define EXT_CSD_ENH_SIZE_MULT 140 /* R/W, 3 bytes */
366#define EXT_CSD_GP_SIZE_MULT 143 /* R/W, 12 bytes */
367#define EXT_CSD_PART_SET 155 /* R/W */
368#define EXT_CSD_PART_ATTR 156 /* R/W */
369#define EXT_CSD_PART_SUPPORT 160 /* RO */
370#define EXT_CSD_RPMB_MULT 168 /* RO */
371#define EXT_CSD_BOOT_WP_STATUS 174 /* RO */
372#define EXT_CSD_ERASE_GRP_DEF 175 /* R/W */
373#define EXT_CSD_PART_CONFIG 179 /* R/W */
374#define EXT_CSD_BUS_WIDTH 183 /* R/W */
375#define EXT_CSD_STROBE_SUPPORT 184 /* RO */
376#define EXT_CSD_HS_TIMING 185 /* R/W */
377#define EXT_CSD_POWER_CLASS 187 /* R/W */
378#define EXT_CSD_CARD_TYPE 196 /* RO */
379#define EXT_CSD_DRIVER_STRENGTH 197 /* RO */
380#define EXT_CSD_REV 192 /* RO */
381#define EXT_CSD_PART_SWITCH_TO 199 /* RO */
382#define EXT_CSD_PWR_CL_52_195 200 /* RO */
383#define EXT_CSD_PWR_CL_26_195 201 /* RO */
384#define EXT_CSD_PWR_CL_52_360 202 /* RO */
385#define EXT_CSD_PWR_CL_26_360 203 /* RO */
386#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
387#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
388#define EXT_CSD_ERASE_TO_MULT 223 /* RO */
389#define EXT_CSD_ERASE_GRP_SIZE 224 /* RO */
390#define EXT_CSD_BOOT_SIZE_MULT 226 /* RO */
391#define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* RO */
392#define EXT_CSD_PWR_CL_200_195 236 /* RO */
393#define EXT_CSD_PWR_CL_200_360 237 /* RO */
394#define EXT_CSD_PWR_CL_52_195_DDR 238 /* RO */
395#define EXT_CSD_PWR_CL_52_360_DDR 239 /* RO */
396#define EXT_CSD_CACHE_FLUSH_POLICY 249 /* RO */
397#define EXT_CSD_GEN_CMD6_TIME 248 /* RO */
398#define EXT_CSD_CACHE_SIZE 249 /* RO, 4 bytes */
399#define EXT_CSD_PWR_CL_200_360_DDR 253 /* RO */
400
401/*
402 * EXT_CSD field definitions
403 */
404#define EXT_CSD_FLUSH_CACHE_FLUSH 0x01
405#define EXT_CSD_FLUSH_CACHE_BARRIER 0x02
406
407#define EXT_CSD_CACHE_CTRL_CACHE_EN 0x01
408
409#define EXT_CSD_EXT_PART_ATTR_DEFAULT 0x0
410#define EXT_CSD_EXT_PART_ATTR_SYSTEMCODE 0x1
411#define EXT_CSD_EXT_PART_ATTR_NPERSISTENT 0x2
412
413#define EXT_CSD_PART_SET_COMPLETED 0x01
414
415#define EXT_CSD_PART_ATTR_ENH_USR 0x01
416#define EXT_CSD_PART_ATTR_ENH_GP0 0x02
417#define EXT_CSD_PART_ATTR_ENH_GP1 0x04
418#define EXT_CSD_PART_ATTR_ENH_GP2 0x08
419#define EXT_CSD_PART_ATTR_ENH_GP3 0x10
420#define EXT_CSD_PART_ATTR_ENH_MASK 0x1f
421
422#define EXT_CSD_PART_SUPPORT_EN 0x01
423#define EXT_CSD_PART_SUPPORT_ENH_ATTR_EN 0x02
424#define EXT_CSD_PART_SUPPORT_EXT_ATTR_EN 0x04
425
426#define EXT_CSD_BOOT_WP_STATUS_BOOT0_PWR 0x01
427#define EXT_CSD_BOOT_WP_STATUS_BOOT0_PERM 0x02
428#define EXT_CSD_BOOT_WP_STATUS_BOOT0_MASK 0x03
429#define EXT_CSD_BOOT_WP_STATUS_BOOT1_PWR 0x04
430#define EXT_CSD_BOOT_WP_STATUS_BOOT1_PERM 0x08
431#define EXT_CSD_BOOT_WP_STATUS_BOOT1_MASK 0x0c
432
433#define EXT_CSD_ERASE_GRP_DEF_EN 0x01
434
435#define EXT_CSD_PART_CONFIG_ACC_DEFAULT 0x00
436#define EXT_CSD_PART_CONFIG_ACC_BOOT0 0x01
437#define EXT_CSD_PART_CONFIG_ACC_BOOT1 0x02
438#define EXT_CSD_PART_CONFIG_ACC_RPMB 0x03
439#define EXT_CSD_PART_CONFIG_ACC_GP0 0x04
440#define EXT_CSD_PART_CONFIG_ACC_GP1 0x05
441#define EXT_CSD_PART_CONFIG_ACC_GP2 0x06
442#define EXT_CSD_PART_CONFIG_ACC_GP3 0x07
443#define EXT_CSD_PART_CONFIG_ACC_MASK 0x07
444#define EXT_CSD_PART_CONFIG_BOOT0 0x08
445#define EXT_CSD_PART_CONFIG_BOOT1 0x10
446#define EXT_CSD_PART_CONFIG_BOOT_USR 0x38
447#define EXT_CSD_PART_CONFIG_BOOT_MASK 0x38
448#define EXT_CSD_PART_CONFIG_BOOT_ACK 0x40
449
450#define EXT_CSD_CMD_SET_NORMAL 1
451#define EXT_CSD_CMD_SET_SECURE 2
452#define EXT_CSD_CMD_SET_CPSECURE 4
453
454#define EXT_CSD_HS_TIMING_BC 0
455#define EXT_CSD_HS_TIMING_HS 1
456#define EXT_CSD_HS_TIMING_HS200 2
457#define EXT_CSD_HS_TIMING_HS400 3
458#define EXT_CSD_HS_TIMING_DRV_STR_SHIFT 4
459
460#define EXT_CSD_POWER_CLASS_8BIT_MASK 0xf0
461#define EXT_CSD_POWER_CLASS_8BIT_SHIFT 4
462#define EXT_CSD_POWER_CLASS_4BIT_MASK 0x0f
463#define EXT_CSD_POWER_CLASS_4BIT_SHIFT 0
464
465#define EXT_CSD_CARD_TYPE_HS_26 0x0001
466#define EXT_CSD_CARD_TYPE_HS_52 0x0002
467#define EXT_CSD_CARD_TYPE_DDR_52_1_8V 0x0004
468#define EXT_CSD_CARD_TYPE_DDR_52_1_2V 0x0008
469#define EXT_CSD_CARD_TYPE_HS200_1_8V 0x0010
470#define EXT_CSD_CARD_TYPE_HS200_1_2V 0x0020
471#define EXT_CSD_CARD_TYPE_HS400_1_8V 0x0040
472#define EXT_CSD_CARD_TYPE_HS400_1_2V 0x0080
473
474#define EXT_CSD_BUS_WIDTH_1 0
475#define EXT_CSD_BUS_WIDTH_4 1
476#define EXT_CSD_BUS_WIDTH_8 2
477#define EXT_CSD_BUS_WIDTH_4_DDR 5
478#define EXT_CSD_BUS_WIDTH_8_DDR 6
479#define EXT_CSD_BUS_WIDTH_ES 0x80
480
481#define EXT_CSD_STROBE_SUPPORT_EN 0x01
482
483#define EXT_CSD_SEC_FEATURE_SUPPORT_ER_EN 0x01
484#define EXT_CSD_SEC_FEATURE_SUPPORT_BD_BLK_EN 0x04
485#define EXT_CSD_SEC_FEATURE_SUPPORT_GB_CL_EN 0x10
486#define EXT_CSD_SEC_FEATURE_SUPPORT_SANITIZE 0x40
487
488#define EXT_CSD_CACHE_FLUSH_POLICY_FIFO 0x01
489
490/*
491 * Vendor specific EXT_CSD fields
492 */
493/* SanDisk iNAND */
494#define EXT_CSD_INAND_CMD38 113
495#define EXT_CSD_INAND_CMD38_ERASE 0x00
496#define EXT_CSD_INAND_CMD38_TRIM 0x01
497#define EXT_CSD_INAND_CMD38_SECURE_ERASE 0x80
498#define EXT_CSD_INAND_CMD38_SECURE_TRIM1 0x81
499#define EXT_CSD_INAND_CMD38_SECURE_TRIM2 0x82
500
501#define MMC_TYPE_HS_26_MAX 26000000
502#define MMC_TYPE_HS_52_MAX 52000000
503#define MMC_TYPE_DDR52_MAX 52000000
504#define MMC_TYPE_HS200_HS400ES_MAX 200000000
505
506/*
507 * SD bus widths
508 */
509#define SD_BUS_WIDTH_1 0
510#define SD_BUS_WIDTH_4 2
511
512/*
513 * SD Switch
514 */
515#define SD_SWITCH_MODE_CHECK 0
516#define SD_SWITCH_MODE_SET 1
517#define SD_SWITCH_GROUP1 0
518#define SD_SWITCH_NORMAL_MODE 0
519#define SD_SWITCH_HS_MODE 1
520#define SD_SWITCH_SDR50_MODE 2
521#define SD_SWITCH_SDR104_MODE 3
522#define SD_SWITCH_DDR50 4
523#define SD_SWITCH_NOCHANGE 0xF
524
525#define SD_CLR_CARD_DETECT 0
526#define SD_SET_CARD_DETECT 1
527
528#define SD_HS_MAX 50000000
529#define SD_DDR50_MAX 50000000
530#define SD_SDR12_MAX 25000000
531#define SD_SDR25_MAX 50000000
532#define SD_SDR50_MAX 100000000
533#define SD_SDR104_MAX 208000000
534
535/* Specifications require 400 kHz max. during ID phase. */
536#define SD_MMC_CARD_ID_FREQUENCY 400000
537
538/*
539 * SDIO Direct & Extended I/O
540 */
541#define SD_IO_RW_WR (1u << 31)
542#define SD_IO_RW_FUNC(x) (((x) & 0x7) << 28)
543#define SD_IO_RW_RAW (1u << 27)
544#define SD_IO_RW_INCR (1u << 26)
545#define SD_IO_RW_ADR(x) (((x) & 0x1FFFF) << 9)
546#define SD_IO_RW_DAT(x) (((x) & 0xFF) << 0)
547#define SD_IO_RW_LEN(x) (((x) & 0xFF) << 0)
548
549#define SD_IOE_RW_LEN(x) (((x) & 0x1FF) << 0)
550#define SD_IOE_RW_ADR(x) (((x) & 0x1FFFF) << 9)
551#define SD_IOE_RW_INCR (1u << 26)
552#define SD_IOE_RW_BLK (1u << 27)
553#define SD_IOE_RW_FUNC(x) (((x) & 0x7) << 28)
554#define SD_IOE_RW_WR (1u << 31)
555
556/* Card Common Control Registers (CCCR) */
557#define SD_IO_CCCR_START 0x00000 /* Offset in F0 address space */
558#define SD_IO_CCCR_SIZE 0x100 /* Total size of CCCR */
559#define SD_IO_CCCR_FN_ENABLE 0x02 /* Enabled functions */
560#define SD_IO_CCCR_FN_READY 0x03 /* Function ready status */
561#define SD_IO_CCCR_INT_ENABLE 0x04 /* Per-function interrupt enable */
562#define SD_IO_CCCR_INT_PENDING 0x05 /* Per-function interrupt pending */
563#define SD_IO_CCCR_CTL 0x06 /* I/O Abort register */
564#define CCCR_CTL_RES (1 << 3) /* Perform SDIO reset */
565#define SD_IO_CCCR_BUS_WIDTH 0x07 /* Bus Width register */
566#define CCCR_BUS_WIDTH_4 (1 << 1)
567#define CCCR_BUS_WIDTH_1 (1 << 0)
568#define SD_IO_CCCR_CARDCAP 0x08 /* SDIO card capabilities */
569#define CCCR_CC_SMB (1 << 1) /* CMD53 block mode support */
570#define CCCR_CC_LSC (1 << 6)
571
572#define SD_IO_CCCR_CISPTR 0x09 /* 0x09 - 0x0B */
573#define SD_IO_CCCR_FN0_BLKSZ 0x10 /* 0x10 - 0x11 */
574#define SD_IO_CCCR_SPEED 0x13
575#define CCCR_SPEED_SHS (1 << 0)
576#define CCCR_SPEED_BSS_MASK (0x7 << 1)
577#define CCCR_SPEED_EHS (1 << 1)
578#define CCCR_SPEED_SDR12 (0 << 1)
579#define CCCR_SPEED_SDR25 (1 << 1)
580#define CCCR_SPEED_SDR50 (2 << 1)
581#define CCCR_SPEED_SDR104 (3 << 1)
582#define CCCR_SPEED_DDR50 (4 << 1)
583
584/* Function Basic Registers (FBR) */
585#define SD_IO_FBR_START 0x00100 /* Offset in F0 address space */
586#define SD_IO_FBR_SIZE 0x00700 /* Total size of FBR */
587#define SD_IO_FBR_F_SIZE 0x00100 /* Size of each function */
588#define SD_IO_FBR_START_F(n) (SD_IO_FBR_START + (n-1) * SD_IO_FBR_F_SIZE)
589#define SD_IO_FBR_CIS_OFFSET 0x9 /* Offset of this function's info block within CIS area */
590#define SD_IO_FBR_IOBLKSZ 0x10 /* Block size for CMD53 block mode operations */
591
592/* Card Information Structure (CIS) */
593#define SD_IO_CIS_START 0x01000 /* Offset in F0 address space */
594#define SD_IO_CIS_SIZE 0x17000 /* Total size of CIS */
595
596/* CIS tuple codes (based on PC Card 16) */
597#define SD_IO_CISTPL_VERS_1 0x15
598#define SD_IO_CISTPL_MANFID 0x20
599#define SD_IO_CISTPL_FUNCID 0x21
600#define SD_IO_CISTPL_FUNCE 0x22
601#define SD_IO_CISTPL_END 0xff
602
603/* CISTPL_FUNCID codes */
604/* OpenBSD incorrectly defines 0x0c as FUNCTION_WLAN */
605/* #define SDMMC_FUNCTION_WLAN 0x0c */
606
607/* OCR bits */
608
609/*
610 * in SD 2.0 spec, bits 8-14 are now marked reserved
611 * Low voltage in SD2.0 spec is bit 7, TBD voltage
612 * Low voltage in MC 3.31 spec is bit 7, 1.65-1.95V
613 * Specs prior to MMC 3.31 defined bits 0-7 as voltages down to 1.5V.
614 * 3.31 redefined them to be reserved and also said that cards had to
615 * support the 2.7-3.6V and fixed the OCR to be 0xfff8000 for high voltage
616 * cards. MMC 4.0 says that a dual voltage card responds with 0xfff8080.
617 * Looks like the fine-grained control of the voltage tolerance ranges
618 * was abandoned.
619 *
620 * The MMC_OCR_CCS appears to be valid for only SD cards.
621 */
622#define MMC_OCR_VOLTAGE 0x3fffffffU /* Vdd Voltage mask */
623#define MMC_OCR_LOW_VOLTAGE (1u << 7) /* Low Voltage Range -- tbd */
624#define MMC_OCR_MIN_VOLTAGE_SHIFT 7
625#define MMC_OCR_200_210 (1U << 8) /* Vdd voltage 2.00 ~ 2.10 */
626#define MMC_OCR_210_220 (1U << 9) /* Vdd voltage 2.10 ~ 2.20 */
627#define MMC_OCR_220_230 (1U << 10) /* Vdd voltage 2.20 ~ 2.30 */
628#define MMC_OCR_230_240 (1U << 11) /* Vdd voltage 2.30 ~ 2.40 */
629#define MMC_OCR_240_250 (1U << 12) /* Vdd voltage 2.40 ~ 2.50 */
630#define MMC_OCR_250_260 (1U << 13) /* Vdd voltage 2.50 ~ 2.60 */
631#define MMC_OCR_260_270 (1U << 14) /* Vdd voltage 2.60 ~ 2.70 */
632#define MMC_OCR_270_280 (1U << 15) /* Vdd voltage 2.70 ~ 2.80 */
633#define MMC_OCR_280_290 (1U << 16) /* Vdd voltage 2.80 ~ 2.90 */
634#define MMC_OCR_290_300 (1U << 17) /* Vdd voltage 2.90 ~ 3.00 */
635#define MMC_OCR_300_310 (1U << 18) /* Vdd voltage 3.00 ~ 3.10 */
636#define MMC_OCR_310_320 (1U << 19) /* Vdd voltage 3.10 ~ 3.20 */
637#define MMC_OCR_320_330 (1U << 20) /* Vdd voltage 3.20 ~ 3.30 */
638#define MMC_OCR_330_340 (1U << 21) /* Vdd voltage 3.30 ~ 3.40 */
639#define MMC_OCR_340_350 (1U << 22) /* Vdd voltage 3.40 ~ 3.50 */
640#define MMC_OCR_350_360 (1U << 23) /* Vdd voltage 3.50 ~ 3.60 */
641#define MMC_OCR_MAX_VOLTAGE_SHIFT 23
642#define MMC_OCR_S18R (1U << 24) /* Switching to 1.8 V requested (SD) */
643#define MMC_OCR_S18A MMC_OCR_S18R /* Switching to 1.8 V accepted (SD) */
644#define MMC_OCR_XPC (1U << 28) /* SDXC Power Control */
645#define MMC_OCR_ACCESS_MODE_BYTE (0U << 29) /* Access Mode Byte (MMC) */
646#define MMC_OCR_ACCESS_MODE_SECT (1U << 29) /* Access Mode Sector (MMC) */
647#define MMC_OCR_ACCESS_MODE_MASK (3U << 29)
648#define MMC_OCR_CCS (1u << 30) /* Card Capacity status (SD vs SDHC) */
649#define MMC_OCR_CARD_BUSY (1U << 31) /* Card Power up status */
650
651/* CSD -- decoded structure */
652struct mmc_cid {
653 uint32_t mid;
654 char pnm[8];
655 uint32_t psn;
656 uint16_t oid;
657 uint16_t mdt_year;
658 uint8_t mdt_month;
659 uint8_t prv;
660 uint8_t fwrev;
661};
662
663struct mmc_csd {
664 uint8_t csd_structure;
665 uint8_t spec_vers;
666 uint16_t ccc;
667 uint16_t tacc;
668 uint32_t nsac;
669 uint32_t r2w_factor;
670 uint32_t tran_speed;
671 uint32_t read_bl_len;
672 uint32_t write_bl_len;
673 uint32_t vdd_r_curr_min;
674 uint32_t vdd_r_curr_max;
675 uint32_t vdd_w_curr_min;
676 uint32_t vdd_w_curr_max;
677 uint32_t wp_grp_size;
678 uint32_t erase_sector;
679 uint64_t capacity;
680 unsigned int read_bl_partial:1,
681 read_blk_misalign:1,
682 write_bl_partial:1,
683 write_blk_misalign:1,
684 dsr_imp:1,
685 erase_blk_en:1,
686 wp_grp_enable:1;
687};
688
689struct mmc_scr {
690 unsigned char sda_vsn;
691 unsigned char bus_widths;
692#define SD_SCR_BUS_WIDTH_1 (1 << 0)
693#define SD_SCR_BUS_WIDTH_4 (1 << 2)
694};
695
696struct mmc_sd_status {
697 uint8_t bus_width;
698 uint8_t secured_mode;
699 uint16_t card_type;
700 uint16_t prot_area;
701 uint8_t speed_class;
702 uint8_t perf_move;
703 uint8_t au_size;
704 uint16_t erase_size;
705 uint8_t erase_timeout;
706 uint8_t erase_offset;
707};
708
709struct mmc_quirk {
710 uint32_t mid;
711#define MMC_QUIRK_MID_ANY ((uint32_t)-1)
712 uint16_t oid;
713#define MMC_QUIRK_OID_ANY ((uint16_t)-1)
714 const char *pnm;
715 uint32_t quirks;
716#define MMC_QUIRK_INAND_CMD38 0x0001
717#define MMC_QUIRK_BROKEN_TRIM 0x0002
718};
719
720#define MMC_QUIRKS_FMT "\020" "\001INAND_CMD38" "\002BROKEN_TRIM"
721
722/*
723 * Various MMC/SD constants
724 */
725#define MMC_BOOT_RPMB_BLOCK_SIZE (128 * 1024)
726
727#define MMC_EXTCSD_SIZE 512
728
729#define MMC_PART_GP_MAX 4
730#define MMC_PART_MAX 8
731
732#define MMC_TUNING_MAX 64 /* Maximum tuning iterations */
733#define MMC_TUNING_LEN 64 /* Size of tuning data */
734#define MMC_TUNING_LEN_HS200 128 /* Size of tuning data in HS200 mode */
735
736/*
737 * Older versions of the MMC standard had a variable sector size. However,
738 * I've been able to find no old MMC or SD cards that have a non 512
739 * byte sector size anywhere, so we assume that such cards are very rare
740 * and only note their existence in passing here...
741 */
742#define MMC_SECTOR_SIZE 512
743
744#endif /* DEV_MMCREG_H */