master
1/*-
2 * SPDX-License-Identifier: BSD-3-Clause
3 *
4 * Copyright (c) 1991 The Regents of the University of California.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of the University nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 * from: @(#)ns16550.h 7.1 (Berkeley) 5/9/91
32 */
33
34/*
35 * NS8250... UART registers.
36 */
37
38/* 8250 registers #[0-6]. */
39
40#define com_data 0 /* data register (R/W) */
41#define REG_DATA com_data
42
43#define com_ier 1 /* interrupt enable register (W) */
44#define REG_IER com_ier
45#define IER_ERXRDY 0x1
46#define IER_ETXRDY 0x2
47#define IER_ERLS 0x4
48#define IER_EMSC 0x8
49/*
50 * Receive timeout interrupt enable.
51 * Implemented in Intel XScale, Ingenic XBurst.
52 */
53#define IER_RXTMOUT 0x10
54
55#define IER_BITS "\20\1ERXRDY\2ETXRDY\3ERLS\4EMSC\5RXTMOUT"
56
57#define com_iir 2 /* interrupt identification register (R) */
58#define REG_IIR com_iir
59#define IIR_IMASK 0xf
60#define IIR_RXTOUT 0xc
61#define IIR_BUSY 0x7
62#define IIR_RLS 0x6
63#define IIR_RXRDY 0x4
64#define IIR_TXRDY 0x2
65#define IIR_NOPEND 0x1
66#define IIR_MLSC 0x0
67#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */
68
69#define IIR_BITS "\20\1NOPEND\2TXRDY\3RXRDY"
70
71#define com_lcr 3 /* line control register (R/W) */
72#define com_cfcr com_lcr /* character format control register (R/W) */
73#define REG_LCR com_lcr
74#define LCR_DLAB 0x80
75#define CFCR_DLAB LCR_DLAB
76#define LCR_EFR_ENABLE 0xbf /* magic to enable EFR on 16650 up */
77#define CFCR_EFR_ENABLE LCR_EFR_ENABLE
78#define LCR_SBREAK 0x40
79#define CFCR_SBREAK LCR_SBREAK
80#define LCR_PZERO 0x30
81#define CFCR_PZERO LCR_PZERO
82#define LCR_PONE 0x20
83#define CFCR_PONE LCR_PONE
84#define LCR_PEVEN 0x10
85#define CFCR_PEVEN LCR_PEVEN
86#define LCR_PODD 0x00
87#define CFCR_PODD LCR_PODD
88#define LCR_PENAB 0x08
89#define CFCR_PENAB LCR_PENAB
90#define LCR_STOPB 0x04
91#define CFCR_STOPB LCR_STOPB
92#define LCR_8BITS 0x03
93#define CFCR_8BITS LCR_8BITS
94#define LCR_7BITS 0x02
95#define CFCR_7BITS LCR_7BITS
96#define LCR_6BITS 0x01
97#define CFCR_6BITS LCR_6BITS
98#define LCR_5BITS 0x00
99#define CFCR_5BITS LCR_5BITS
100
101#define com_mcr 4 /* modem control register (R/W) */
102#define REG_MCR com_mcr
103#define MCR_PRESCALE 0x80 /* only available on 16650 up */
104#define MCR_LOOPBACK 0x10
105#define MCR_IE 0x08
106#define MCR_IENABLE MCR_IE
107#define MCR_DRS 0x04
108#define MCR_RTS 0x02
109#define MCR_DTR 0x01
110
111#define MCR_BITS "\20\1DTR\2RTS\3DRS\4IE\5LOOPBACK\10PRESCALE"
112
113#define com_lsr 5 /* line status register (R/W) */
114#define REG_LSR com_lsr
115#define LSR_RCV_FIFO 0x80
116#define LSR_TEMT 0x40
117#define LSR_TSRE LSR_TEMT
118#define LSR_THRE 0x20
119#define LSR_TXRDY LSR_THRE
120#define LSR_BI 0x10
121#define LSR_FE 0x08
122#define LSR_PE 0x04
123#define LSR_OE 0x02
124#define LSR_RXRDY 0x01
125#define LSR_RCV_MASK 0x1f
126
127#define LSR_BITS "\20\1RXRDY\2OE\3PE\4FE\5BI\6THRE\7TEMT\10RCV_FIFO"
128
129#define com_msr 6 /* modem status register (R/W) */
130#define REG_MSR com_msr
131#define MSR_DCD 0x80
132#define MSR_RI 0x40
133#define MSR_DSR 0x20
134#define MSR_CTS 0x10
135#define MSR_DDCD 0x08
136#define MSR_TERI 0x04
137#define MSR_DDSR 0x02
138#define MSR_DCTS 0x01
139
140#define MSR_BITS "\20\1DCTS\2DDSR\3TERI\4DDCD\5CTS\6DSR\7RI\10DCD"
141
142/* 8250 multiplexed registers #[0-1]. Access enabled by LCR[7]. */
143#define com_dll 0 /* divisor latch low (R/W) */
144#define com_dlbl com_dll
145#define com_dlm 1 /* divisor latch high (R/W) */
146#define com_dlbh com_dlm
147#define REG_DLL com_dll
148#define REG_DLH com_dlm
149
150/* 16450 register #7. Not multiplexed. */
151#define com_scr 7 /* scratch register (R/W) */
152
153/* 16550 register #2. Not multiplexed. */
154#define com_fcr 2 /* FIFO control register (W) */
155#define com_fifo com_fcr
156#define REG_FCR com_fcr
157#define FCR_ENABLE 0x01
158#define FIFO_ENABLE FCR_ENABLE
159#define FCR_RCV_RST 0x02
160#define FIFO_RCV_RST FCR_RCV_RST
161#define FCR_XMT_RST 0x04
162#define FIFO_XMT_RST FCR_XMT_RST
163#define FCR_DMA 0x08
164#define FIFO_DMA_MODE FCR_DMA
165#ifdef CPU_XBURST
166#define FCR_UART_ON 0x10
167#endif
168#define FCR_RX_LOW 0x00
169#define FIFO_RX_LOW FCR_RX_LOW
170#define FCR_RX_MEDL 0x40
171#define FIFO_RX_MEDL FCR_RX_MEDL
172#define FCR_RX_MEDH 0x80
173#define FIFO_RX_MEDH FCR_RX_MEDH
174#define FCR_RX_HIGH 0xc0
175#define FIFO_RX_HIGH FCR_RX_HIGH
176
177#define FCR_BITS "\20\1ENABLE\2RCV_RST\3XMT_RST\4DMA"
178
179/* 16650 registers #2,[4-7]. Access enabled by LCR_EFR_ENABLE. */
180
181#define com_efr 2 /* enhanced features register (R/W) */
182#define REG_EFR com_efr
183#define EFR_CTS 0x80
184#define EFR_AUTOCTS EFR_CTS
185#define EFR_RTS 0x40
186#define EFR_AUTORTS EFR_RTS
187#define EFR_EFE 0x10 /* enhanced functions enable */
188
189#define com_xon1 4 /* XON 1 character (R/W) */
190#define com_xon2 5 /* XON 2 character (R/W) */
191#define com_xoff1 6 /* XOFF 1 character (R/W) */
192#define com_xoff2 7 /* XOFF 2 character (R/W) */
193
194#define DW_REG_USR 31 /* DesignWare derived Uart Status Reg */
195#define com_usr 39 /* Octeon 16750/16550 Uart Status Reg */
196#define REG_USR com_usr
197#define USR_BUSY 1 /* Uart Busy. Serial transfer in progress */
198#define USR_TXFIFO_NOTFULL 2 /* Uart TX FIFO Not full */
199
200/* 16950 register #1. Access enabled by ACR[7]. Also requires !LCR[7]. */
201#define com_asr 1 /* additional status register (R[0-7]/W[0-1]) */
202
203/* 16950 register #3. R/W access enabled by ACR[7]. */
204#define com_rfl 3 /* receiver fifo level (R) */
205
206/*
207 * 16950 register #4. Access enabled by ACR[7]. Also requires
208 * !LCR_EFR_ENABLE.
209 */
210#define com_tfl 4 /* transmitter fifo level (R) */
211
212/*
213 * 16950 register #5. Accessible if !LCR_EFR_ENABLE. Read access also
214 * requires ACR[6].
215 */
216#define com_icr 5 /* index control register (R/W) */
217#define REG_ICR com_icr
218
219/*
220 * 16950 register #7. It is the same as com_scr except it has a different
221 * abbreviation in the manufacturer's data sheet and it also serves as an
222 * index into the Indexed Control register set.
223 */
224#define com_spr com_scr /* scratch pad (and index) register (R/W) */
225#define REG_SPR com_scr
226
227/*
228 * 16950 indexed control registers #[0-0x13]. Access is via index in SPR,
229 * data in ICR (if ICR is accessible).
230 */
231
232#define com_acr 0 /* additional control register (R/W) */
233#define REG_ACR com_acr
234#define ACR_ASE 0x80 /* ASR/RFL/TFL enable */
235#define ACR_ICRE 0x40 /* ICR enable */
236#define ACR_TLE 0x20 /* TTL/RTL enable */
237
238#define com_cpr 1 /* clock prescaler register (R/W) */
239#define com_tcr 2 /* times clock register (R/W) */
240#define com_ttl 4 /* transmitter trigger level (R/W) */
241#define com_rtl 5 /* receiver trigger level (R/W) */
242/* ... */
243
244/* Hardware extension mode register for RSB-2000/3000. */
245#define com_emr com_msr
246#define EMR_EXBUFF 0x04
247#define EMR_CTSFLW 0x08
248#define EMR_DSRFLW 0x10
249#define EMR_RTSFLW 0x20
250#define EMR_DTRFLW 0x40
251#define EMR_EFMODE 0x80