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1/*
2 * Virtio PCI driver
3 *
4 * This module allows virtio devices to be used over a virtual PCI device.
5 * This can be used with QEMU based VMMs like KVM or Xen.
6 *
7 * Copyright IBM Corp. 2007
8 *
9 * Authors:
10 * Anthony Liguori <aliguori@us.ibm.com>
11 *
12 * This header is BSD licensed so anyone can use the definitions to implement
13 * compatible drivers/servers.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 * 3. Neither the name of IBM nor the names of its contributors
24 * may be used to endorse or promote products derived from this software
25 * without specific prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL IBM OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * SUCH DAMAGE.
37 */
38
39#ifndef _LINUX_VIRTIO_PCI_H
40#define _LINUX_VIRTIO_PCI_H
41
42#include <linux/types.h>
43#include <linux/kernel.h>
44
45#ifndef VIRTIO_PCI_NO_LEGACY
46
47/* A 32-bit r/o bitmask of the features supported by the host */
48#define VIRTIO_PCI_HOST_FEATURES 0
49
50/* A 32-bit r/w bitmask of features activated by the guest */
51#define VIRTIO_PCI_GUEST_FEATURES 4
52
53/* A 32-bit r/w PFN for the currently selected queue */
54#define VIRTIO_PCI_QUEUE_PFN 8
55
56/* A 16-bit r/o queue size for the currently selected queue */
57#define VIRTIO_PCI_QUEUE_NUM 12
58
59/* A 16-bit r/w queue selector */
60#define VIRTIO_PCI_QUEUE_SEL 14
61
62/* A 16-bit r/w queue notifier */
63#define VIRTIO_PCI_QUEUE_NOTIFY 16
64
65/* An 8-bit device status register. */
66#define VIRTIO_PCI_STATUS 18
67
68/* An 8-bit r/o interrupt status register. Reading the value will return the
69 * current contents of the ISR and will also clear it. This is effectively
70 * a read-and-acknowledge. */
71#define VIRTIO_PCI_ISR 19
72
73/* MSI-X registers: only enabled if MSI-X is enabled. */
74/* A 16-bit vector for configuration changes. */
75#define VIRTIO_MSI_CONFIG_VECTOR 20
76/* A 16-bit vector for selected queue notifications. */
77#define VIRTIO_MSI_QUEUE_VECTOR 22
78
79/* The remaining space is defined by each driver as the per-driver
80 * configuration space */
81#define VIRTIO_PCI_CONFIG_OFF(msix_enabled) ((msix_enabled) ? 24 : 20)
82/* Deprecated: please use VIRTIO_PCI_CONFIG_OFF instead */
83#define VIRTIO_PCI_CONFIG(dev) VIRTIO_PCI_CONFIG_OFF((dev)->msix_enabled)
84
85/* Virtio ABI version, this must match exactly */
86#define VIRTIO_PCI_ABI_VERSION 0
87
88/* How many bits to shift physical queue address written to QUEUE_PFN.
89 * 12 is historical, and due to x86 page size. */
90#define VIRTIO_PCI_QUEUE_ADDR_SHIFT 12
91
92/* The alignment to use between consumer and producer parts of vring.
93 * x86 pagesize again. */
94#define VIRTIO_PCI_VRING_ALIGN 4096
95
96#endif /* VIRTIO_PCI_NO_LEGACY */
97
98/* The bit of the ISR which indicates a device configuration change. */
99#define VIRTIO_PCI_ISR_CONFIG 0x2
100/* Vector value used to disable MSI for queue */
101#define VIRTIO_MSI_NO_VECTOR 0xffff
102
103#ifndef VIRTIO_PCI_NO_MODERN
104
105/* IDs for different capabilities. Must all exist. */
106
107/* Common configuration */
108#define VIRTIO_PCI_CAP_COMMON_CFG 1
109/* Notifications */
110#define VIRTIO_PCI_CAP_NOTIFY_CFG 2
111/* ISR access */
112#define VIRTIO_PCI_CAP_ISR_CFG 3
113/* Device specific configuration */
114#define VIRTIO_PCI_CAP_DEVICE_CFG 4
115/* PCI configuration access */
116#define VIRTIO_PCI_CAP_PCI_CFG 5
117/* Additional shared memory capability */
118#define VIRTIO_PCI_CAP_SHARED_MEMORY_CFG 8
119/* PCI vendor data configuration */
120#define VIRTIO_PCI_CAP_VENDOR_CFG 9
121
122/* This is the PCI capability header: */
123struct virtio_pci_cap {
124 __u8 cap_vndr; /* Generic PCI field: PCI_CAP_ID_VNDR */
125 __u8 cap_next; /* Generic PCI field: next ptr. */
126 __u8 cap_len; /* Generic PCI field: capability length */
127 __u8 cfg_type; /* Identifies the structure. */
128 __u8 bar; /* Where to find it. */
129 __u8 id; /* Multiple capabilities of the same type */
130 __u8 padding[2]; /* Pad to full dword. */
131 __le32 offset; /* Offset within bar. */
132 __le32 length; /* Length of the structure, in bytes. */
133};
134
135/* This is the PCI vendor data capability header: */
136struct virtio_pci_vndr_data {
137 __u8 cap_vndr; /* Generic PCI field: PCI_CAP_ID_VNDR */
138 __u8 cap_next; /* Generic PCI field: next ptr. */
139 __u8 cap_len; /* Generic PCI field: capability length */
140 __u8 cfg_type; /* Identifies the structure. */
141 __u16 vendor_id; /* Identifies the vendor-specific format. */
142 /* For Vendor Definition */
143 /* Pads structure to a multiple of 4 bytes */
144 /* Reads must not have side effects */
145};
146
147struct virtio_pci_cap64 {
148 struct virtio_pci_cap cap;
149 __le32 offset_hi; /* Most sig 32 bits of offset */
150 __le32 length_hi; /* Most sig 32 bits of length */
151};
152
153struct virtio_pci_notify_cap {
154 struct virtio_pci_cap cap;
155 __le32 notify_off_multiplier; /* Multiplier for queue_notify_off. */
156};
157
158/* Fields in VIRTIO_PCI_CAP_COMMON_CFG: */
159struct virtio_pci_common_cfg {
160 /* About the whole device. */
161 __le32 device_feature_select; /* read-write */
162 __le32 device_feature; /* read-only */
163 __le32 guest_feature_select; /* read-write */
164 __le32 guest_feature; /* read-write */
165 __le16 msix_config; /* read-write */
166 __le16 num_queues; /* read-only */
167 __u8 device_status; /* read-write */
168 __u8 config_generation; /* read-only */
169
170 /* About a specific virtqueue. */
171 __le16 queue_select; /* read-write */
172 __le16 queue_size; /* read-write, power of 2. */
173 __le16 queue_msix_vector; /* read-write */
174 __le16 queue_enable; /* read-write */
175 __le16 queue_notify_off; /* read-only */
176 __le32 queue_desc_lo; /* read-write */
177 __le32 queue_desc_hi; /* read-write */
178 __le32 queue_avail_lo; /* read-write */
179 __le32 queue_avail_hi; /* read-write */
180 __le32 queue_used_lo; /* read-write */
181 __le32 queue_used_hi; /* read-write */
182};
183
184/*
185 * Warning: do not use sizeof on this: use offsetofend for
186 * specific fields you need.
187 */
188struct virtio_pci_modern_common_cfg {
189 struct virtio_pci_common_cfg cfg;
190
191 __le16 queue_notify_data; /* read-write */
192 __le16 queue_reset; /* read-write */
193
194 __le16 admin_queue_index; /* read-only */
195 __le16 admin_queue_num; /* read-only */
196};
197
198/* Fields in VIRTIO_PCI_CAP_PCI_CFG: */
199struct virtio_pci_cfg_cap {
200 struct virtio_pci_cap cap;
201 __u8 pci_cfg_data[4]; /* Data for BAR access. */
202};
203
204/* Macro versions of offsets for the Old Timers! */
205#define VIRTIO_PCI_CAP_VNDR 0
206#define VIRTIO_PCI_CAP_NEXT 1
207#define VIRTIO_PCI_CAP_LEN 2
208#define VIRTIO_PCI_CAP_CFG_TYPE 3
209#define VIRTIO_PCI_CAP_BAR 4
210#define VIRTIO_PCI_CAP_OFFSET 8
211#define VIRTIO_PCI_CAP_LENGTH 12
212
213#define VIRTIO_PCI_NOTIFY_CAP_MULT 16
214
215#define VIRTIO_PCI_COMMON_DFSELECT 0
216#define VIRTIO_PCI_COMMON_DF 4
217#define VIRTIO_PCI_COMMON_GFSELECT 8
218#define VIRTIO_PCI_COMMON_GF 12
219#define VIRTIO_PCI_COMMON_MSIX 16
220#define VIRTIO_PCI_COMMON_NUMQ 18
221#define VIRTIO_PCI_COMMON_STATUS 20
222#define VIRTIO_PCI_COMMON_CFGGENERATION 21
223#define VIRTIO_PCI_COMMON_Q_SELECT 22
224#define VIRTIO_PCI_COMMON_Q_SIZE 24
225#define VIRTIO_PCI_COMMON_Q_MSIX 26
226#define VIRTIO_PCI_COMMON_Q_ENABLE 28
227#define VIRTIO_PCI_COMMON_Q_NOFF 30
228#define VIRTIO_PCI_COMMON_Q_DESCLO 32
229#define VIRTIO_PCI_COMMON_Q_DESCHI 36
230#define VIRTIO_PCI_COMMON_Q_AVAILLO 40
231#define VIRTIO_PCI_COMMON_Q_AVAILHI 44
232#define VIRTIO_PCI_COMMON_Q_USEDLO 48
233#define VIRTIO_PCI_COMMON_Q_USEDHI 52
234#define VIRTIO_PCI_COMMON_Q_NDATA 56
235#define VIRTIO_PCI_COMMON_Q_RESET 58
236#define VIRTIO_PCI_COMMON_ADM_Q_IDX 60
237#define VIRTIO_PCI_COMMON_ADM_Q_NUM 62
238
239#endif /* VIRTIO_PCI_NO_MODERN */
240
241/* Admin command status. */
242#define VIRTIO_ADMIN_STATUS_OK 0
243
244/* Admin command opcode. */
245#define VIRTIO_ADMIN_CMD_LIST_QUERY 0x0
246#define VIRTIO_ADMIN_CMD_LIST_USE 0x1
247
248/* Admin command group type. */
249#define VIRTIO_ADMIN_GROUP_TYPE_SELF 0x0
250#define VIRTIO_ADMIN_GROUP_TYPE_SRIOV 0x1
251
252/* Transitional device admin command. */
253#define VIRTIO_ADMIN_CMD_LEGACY_COMMON_CFG_WRITE 0x2
254#define VIRTIO_ADMIN_CMD_LEGACY_COMMON_CFG_READ 0x3
255#define VIRTIO_ADMIN_CMD_LEGACY_DEV_CFG_WRITE 0x4
256#define VIRTIO_ADMIN_CMD_LEGACY_DEV_CFG_READ 0x5
257#define VIRTIO_ADMIN_CMD_LEGACY_NOTIFY_INFO 0x6
258
259/* Device parts access commands. */
260#define VIRTIO_ADMIN_CMD_CAP_ID_LIST_QUERY 0x7
261#define VIRTIO_ADMIN_CMD_DEVICE_CAP_GET 0x8
262#define VIRTIO_ADMIN_CMD_DRIVER_CAP_SET 0x9
263#define VIRTIO_ADMIN_CMD_RESOURCE_OBJ_CREATE 0xa
264#define VIRTIO_ADMIN_CMD_RESOURCE_OBJ_DESTROY 0xd
265#define VIRTIO_ADMIN_CMD_DEV_PARTS_METADATA_GET 0xe
266#define VIRTIO_ADMIN_CMD_DEV_PARTS_GET 0xf
267#define VIRTIO_ADMIN_CMD_DEV_PARTS_SET 0x10
268#define VIRTIO_ADMIN_CMD_DEV_MODE_SET 0x11
269
270struct virtio_admin_cmd_hdr {
271 __le16 opcode;
272 /*
273 * 1 - SR-IOV
274 * 2-65535 - reserved
275 */
276 __le16 group_type;
277 /* Unused, reserved for future extensions. */
278 __u8 reserved1[12];
279 __le64 group_member_id;
280};
281
282struct virtio_admin_cmd_status {
283 __le16 status;
284 __le16 status_qualifier;
285 /* Unused, reserved for future extensions. */
286 __u8 reserved2[4];
287};
288
289struct virtio_admin_cmd_legacy_wr_data {
290 __u8 offset; /* Starting offset of the register(s) to write. */
291 __u8 reserved[7];
292 __u8 registers[];
293};
294
295struct virtio_admin_cmd_legacy_rd_data {
296 __u8 offset; /* Starting offset of the register(s) to read. */
297};
298
299#define VIRTIO_ADMIN_CMD_NOTIFY_INFO_FLAGS_END 0
300#define VIRTIO_ADMIN_CMD_NOTIFY_INFO_FLAGS_OWNER_DEV 0x1
301#define VIRTIO_ADMIN_CMD_NOTIFY_INFO_FLAGS_OWNER_MEM 0x2
302
303#define VIRTIO_ADMIN_CMD_MAX_NOTIFY_INFO 4
304
305struct virtio_admin_cmd_notify_info_data {
306 __u8 flags; /* 0 = end of list, 1 = owner device, 2 = member device */
307 __u8 bar; /* BAR of the member or the owner device */
308 __u8 padding[6];
309 __le64 offset; /* Offset within bar. */
310};
311
312struct virtio_admin_cmd_notify_info_result {
313 struct virtio_admin_cmd_notify_info_data entries[VIRTIO_ADMIN_CMD_MAX_NOTIFY_INFO];
314};
315
316#define VIRTIO_DEV_PARTS_CAP 0x0000
317
318struct virtio_dev_parts_cap {
319 __u8 get_parts_resource_objects_limit;
320 __u8 set_parts_resource_objects_limit;
321};
322
323#define MAX_CAP_ID __KERNEL_DIV_ROUND_UP(VIRTIO_DEV_PARTS_CAP + 1, 64)
324
325struct virtio_admin_cmd_query_cap_id_result {
326 __le64 supported_caps[MAX_CAP_ID];
327};
328
329struct virtio_admin_cmd_cap_get_data {
330 __le16 id;
331 __u8 reserved[6];
332};
333
334struct virtio_admin_cmd_cap_set_data {
335 __le16 id;
336 __u8 reserved[6];
337 __u8 cap_specific_data[];
338};
339
340struct virtio_admin_cmd_resource_obj_cmd_hdr {
341 __le16 type;
342 __u8 reserved[2];
343 __le32 id; /* Indicates unique resource object id per resource object type */
344};
345
346struct virtio_admin_cmd_resource_obj_create_data {
347 struct virtio_admin_cmd_resource_obj_cmd_hdr hdr;
348 __le64 flags;
349 __u8 resource_obj_specific_data[];
350};
351
352#define VIRTIO_RESOURCE_OBJ_DEV_PARTS 0
353
354#define VIRTIO_RESOURCE_OBJ_DEV_PARTS_TYPE_GET 0
355#define VIRTIO_RESOURCE_OBJ_DEV_PARTS_TYPE_SET 1
356
357struct virtio_resource_obj_dev_parts {
358 __u8 type;
359 __u8 reserved[7];
360};
361
362#define VIRTIO_ADMIN_CMD_DEV_PARTS_METADATA_TYPE_SIZE 0
363#define VIRTIO_ADMIN_CMD_DEV_PARTS_METADATA_TYPE_COUNT 1
364#define VIRTIO_ADMIN_CMD_DEV_PARTS_METADATA_TYPE_LIST 2
365
366struct virtio_admin_cmd_dev_parts_metadata_data {
367 struct virtio_admin_cmd_resource_obj_cmd_hdr hdr;
368 __u8 type;
369 __u8 reserved[7];
370};
371
372#define VIRTIO_DEV_PART_F_OPTIONAL 0
373
374struct virtio_dev_part_hdr {
375 __le16 part_type;
376 __u8 flags;
377 __u8 reserved;
378 union {
379 struct {
380 __le32 offset;
381 __le32 reserved;
382 } pci_common_cfg;
383 struct {
384 __le16 index;
385 __u8 reserved[6];
386 } vq_index;
387 } selector;
388 __le32 length;
389};
390
391struct virtio_dev_part {
392 struct virtio_dev_part_hdr hdr;
393 __u8 value[];
394};
395
396struct virtio_admin_cmd_dev_parts_metadata_result {
397 union {
398 struct {
399 __le32 size;
400 __le32 reserved;
401 } parts_size;
402 struct {
403 __le32 count;
404 __le32 reserved;
405 } hdr_list_count;
406 struct {
407 __le32 count;
408 __le32 reserved;
409 struct virtio_dev_part_hdr hdrs[];
410 } hdr_list;
411 };
412};
413
414#define VIRTIO_ADMIN_CMD_DEV_PARTS_GET_TYPE_SELECTED 0
415#define VIRTIO_ADMIN_CMD_DEV_PARTS_GET_TYPE_ALL 1
416
417struct virtio_admin_cmd_dev_parts_get_data {
418 struct virtio_admin_cmd_resource_obj_cmd_hdr hdr;
419 __u8 type;
420 __u8 reserved[7];
421 struct virtio_dev_part_hdr hdr_list[];
422};
423
424struct virtio_admin_cmd_dev_parts_set_data {
425 struct virtio_admin_cmd_resource_obj_cmd_hdr hdr;
426 struct virtio_dev_part parts[];
427};
428
429#define VIRTIO_ADMIN_CMD_DEV_MODE_F_STOPPED 0
430
431struct virtio_admin_cmd_dev_mode_set_data {
432 __u8 flags;
433};
434
435#endif