master
1/*
2 * Copyright © 2014-2018 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24#ifndef _V3D_DRM_H_
25#define _V3D_DRM_H_
26
27#include "drm.h"
28
29#if defined(__cplusplus)
30extern "C" {
31#endif
32
33#define DRM_V3D_SUBMIT_CL 0x00
34#define DRM_V3D_WAIT_BO 0x01
35#define DRM_V3D_CREATE_BO 0x02
36#define DRM_V3D_MMAP_BO 0x03
37#define DRM_V3D_GET_PARAM 0x04
38#define DRM_V3D_GET_BO_OFFSET 0x05
39#define DRM_V3D_SUBMIT_TFU 0x06
40#define DRM_V3D_SUBMIT_CSD 0x07
41#define DRM_V3D_PERFMON_CREATE 0x08
42#define DRM_V3D_PERFMON_DESTROY 0x09
43#define DRM_V3D_PERFMON_GET_VALUES 0x0a
44#define DRM_V3D_SUBMIT_CPU 0x0b
45#define DRM_V3D_PERFMON_GET_COUNTER 0x0c
46#define DRM_V3D_PERFMON_SET_GLOBAL 0x0d
47
48#define DRM_IOCTL_V3D_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl)
49#define DRM_IOCTL_V3D_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo)
50#define DRM_IOCTL_V3D_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_CREATE_BO, struct drm_v3d_create_bo)
51#define DRM_IOCTL_V3D_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_MMAP_BO, struct drm_v3d_mmap_bo)
52#define DRM_IOCTL_V3D_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_PARAM, struct drm_v3d_get_param)
53#define DRM_IOCTL_V3D_GET_BO_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_BO_OFFSET, struct drm_v3d_get_bo_offset)
54#define DRM_IOCTL_V3D_SUBMIT_TFU DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_TFU, struct drm_v3d_submit_tfu)
55#define DRM_IOCTL_V3D_SUBMIT_CSD DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CSD, struct drm_v3d_submit_csd)
56#define DRM_IOCTL_V3D_PERFMON_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_CREATE, \
57 struct drm_v3d_perfmon_create)
58#define DRM_IOCTL_V3D_PERFMON_DESTROY DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_DESTROY, \
59 struct drm_v3d_perfmon_destroy)
60#define DRM_IOCTL_V3D_PERFMON_GET_VALUES DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_GET_VALUES, \
61 struct drm_v3d_perfmon_get_values)
62#define DRM_IOCTL_V3D_SUBMIT_CPU DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CPU, struct drm_v3d_submit_cpu)
63#define DRM_IOCTL_V3D_PERFMON_GET_COUNTER DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_GET_COUNTER, \
64 struct drm_v3d_perfmon_get_counter)
65#define DRM_IOCTL_V3D_PERFMON_SET_GLOBAL DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_PERFMON_SET_GLOBAL, \
66 struct drm_v3d_perfmon_set_global)
67
68#define DRM_V3D_SUBMIT_CL_FLUSH_CACHE 0x01
69#define DRM_V3D_SUBMIT_EXTENSION 0x02
70
71/* struct drm_v3d_extension - ioctl extensions
72 *
73 * Linked-list of generic extensions where the id identify which struct is
74 * pointed by ext_data. Therefore, DRM_V3D_EXT_ID_* is used on id to identify
75 * the extension type.
76 */
77struct drm_v3d_extension {
78 __u64 next;
79 __u32 id;
80#define DRM_V3D_EXT_ID_MULTI_SYNC 0x01
81#define DRM_V3D_EXT_ID_CPU_INDIRECT_CSD 0x02
82#define DRM_V3D_EXT_ID_CPU_TIMESTAMP_QUERY 0x03
83#define DRM_V3D_EXT_ID_CPU_RESET_TIMESTAMP_QUERY 0x04
84#define DRM_V3D_EXT_ID_CPU_COPY_TIMESTAMP_QUERY 0x05
85#define DRM_V3D_EXT_ID_CPU_RESET_PERFORMANCE_QUERY 0x06
86#define DRM_V3D_EXT_ID_CPU_COPY_PERFORMANCE_QUERY 0x07
87 __u32 flags; /* mbz */
88};
89
90/* struct drm_v3d_sem - wait/signal semaphore
91 *
92 * If binary semaphore, it only takes syncobj handle and ignores flags and
93 * point fields. Point is defined for timeline syncobj feature.
94 */
95struct drm_v3d_sem {
96 __u32 handle; /* syncobj */
97 /* rsv below, for future uses */
98 __u32 flags;
99 __u64 point; /* for timeline sem support */
100 __u64 mbz[2]; /* must be zero, rsv */
101};
102
103/* Enum for each of the V3D queues. */
104enum v3d_queue {
105 V3D_BIN,
106 V3D_RENDER,
107 V3D_TFU,
108 V3D_CSD,
109 V3D_CACHE_CLEAN,
110 V3D_CPU,
111};
112
113/**
114 * struct drm_v3d_multi_sync - ioctl extension to add support multiples
115 * syncobjs for commands submission.
116 *
117 * When an extension of DRM_V3D_EXT_ID_MULTI_SYNC id is defined, it points to
118 * this extension to define wait and signal dependencies, instead of single
119 * in/out sync entries on submitting commands. The field flags is used to
120 * determine the stage to set wait dependencies.
121 */
122struct drm_v3d_multi_sync {
123 struct drm_v3d_extension base;
124 /* Array of wait and signal semaphores */
125 __u64 in_syncs;
126 __u64 out_syncs;
127
128 /* Number of entries */
129 __u32 in_sync_count;
130 __u32 out_sync_count;
131
132 /* set the stage (v3d_queue) to sync */
133 __u32 wait_stage;
134
135 __u32 pad; /* mbz */
136};
137
138/**
139 * struct drm_v3d_submit_cl - ioctl argument for submitting commands to the 3D
140 * engine.
141 *
142 * This asks the kernel to have the GPU execute an optional binner
143 * command list, and a render command list.
144 *
145 * The L1T, slice, L2C, L2T, and GCA caches will be flushed before
146 * each CL executes. The VCD cache should be flushed (if necessary)
147 * by the submitted CLs. The TLB writes are guaranteed to have been
148 * flushed by the time the render done IRQ happens, which is the
149 * trigger for out_sync. Any dirtying of cachelines by the job (only
150 * possible using TMU writes) must be flushed by the caller using the
151 * DRM_V3D_SUBMIT_CL_FLUSH_CACHE_FLAG flag.
152 */
153struct drm_v3d_submit_cl {
154 /* Pointer to the binner command list.
155 *
156 * This is the first set of commands executed, which runs the
157 * coordinate shader to determine where primitives land on the screen,
158 * then writes out the state updates and draw calls necessary per tile
159 * to the tile allocation BO.
160 *
161 * This BCL will block on any previous BCL submitted on the
162 * same FD, but not on any RCL or BCLs submitted by other
163 * clients -- that is left up to the submitter to control
164 * using in_sync_bcl if necessary.
165 */
166 __u32 bcl_start;
167
168 /** End address of the BCL (first byte after the BCL) */
169 __u32 bcl_end;
170
171 /* Offset of the render command list.
172 *
173 * This is the second set of commands executed, which will either
174 * execute the tiles that have been set up by the BCL, or a fixed set
175 * of tiles (in the case of RCL-only blits).
176 *
177 * This RCL will block on this submit's BCL, and any previous
178 * RCL submitted on the same FD, but not on any RCL or BCLs
179 * submitted by other clients -- that is left up to the
180 * submitter to control using in_sync_rcl if necessary.
181 */
182 __u32 rcl_start;
183
184 /** End address of the RCL (first byte after the RCL) */
185 __u32 rcl_end;
186
187 /** An optional sync object to wait on before starting the BCL. */
188 __u32 in_sync_bcl;
189 /** An optional sync object to wait on before starting the RCL. */
190 __u32 in_sync_rcl;
191 /** An optional sync object to place the completion fence in. */
192 __u32 out_sync;
193
194 /* Offset of the tile alloc memory
195 *
196 * This is optional on V3D 3.3 (where the CL can set the value) but
197 * required on V3D 4.1.
198 */
199 __u32 qma;
200
201 /** Size of the tile alloc memory. */
202 __u32 qms;
203
204 /** Offset of the tile state data array. */
205 __u32 qts;
206
207 /* Pointer to a u32 array of the BOs that are referenced by the job.
208 */
209 __u64 bo_handles;
210
211 /* Number of BO handles passed in (size is that times 4). */
212 __u32 bo_handle_count;
213
214 /* DRM_V3D_SUBMIT_* properties */
215 __u32 flags;
216
217 /* ID of the perfmon to attach to this job. 0 means no perfmon. */
218 __u32 perfmon_id;
219
220 __u32 pad;
221
222 /* Pointer to an array of ioctl extensions*/
223 __u64 extensions;
224};
225
226/**
227 * struct drm_v3d_wait_bo - ioctl argument for waiting for
228 * completion of the last DRM_V3D_SUBMIT_CL on a BO.
229 *
230 * This is useful for cases where multiple processes might be
231 * rendering to a BO and you want to wait for all rendering to be
232 * completed.
233 */
234struct drm_v3d_wait_bo {
235 __u32 handle;
236 __u32 pad;
237 __u64 timeout_ns;
238};
239
240/**
241 * struct drm_v3d_create_bo - ioctl argument for creating V3D BOs.
242 *
243 * There are currently no values for the flags argument, but it may be
244 * used in a future extension.
245 */
246struct drm_v3d_create_bo {
247 __u32 size;
248 __u32 flags;
249 /** Returned GEM handle for the BO. */
250 __u32 handle;
251 /**
252 * Returned offset for the BO in the V3D address space. This offset
253 * is private to the DRM fd and is valid for the lifetime of the GEM
254 * handle.
255 *
256 * This offset value will always be nonzero, since various HW
257 * units treat 0 specially.
258 */
259 __u32 offset;
260};
261
262/**
263 * struct drm_v3d_mmap_bo - ioctl argument for mapping V3D BOs.
264 *
265 * This doesn't actually perform an mmap. Instead, it returns the
266 * offset you need to use in an mmap on the DRM device node. This
267 * means that tools like valgrind end up knowing about the mapped
268 * memory.
269 *
270 * There are currently no values for the flags argument, but it may be
271 * used in a future extension.
272 */
273struct drm_v3d_mmap_bo {
274 /** Handle for the object being mapped. */
275 __u32 handle;
276 __u32 flags;
277 /** offset into the drm node to use for subsequent mmap call. */
278 __u64 offset;
279};
280
281enum drm_v3d_param {
282 DRM_V3D_PARAM_V3D_UIFCFG,
283 DRM_V3D_PARAM_V3D_HUB_IDENT1,
284 DRM_V3D_PARAM_V3D_HUB_IDENT2,
285 DRM_V3D_PARAM_V3D_HUB_IDENT3,
286 DRM_V3D_PARAM_V3D_CORE0_IDENT0,
287 DRM_V3D_PARAM_V3D_CORE0_IDENT1,
288 DRM_V3D_PARAM_V3D_CORE0_IDENT2,
289 DRM_V3D_PARAM_SUPPORTS_TFU,
290 DRM_V3D_PARAM_SUPPORTS_CSD,
291 DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH,
292 DRM_V3D_PARAM_SUPPORTS_PERFMON,
293 DRM_V3D_PARAM_SUPPORTS_MULTISYNC_EXT,
294 DRM_V3D_PARAM_SUPPORTS_CPU_QUEUE,
295 DRM_V3D_PARAM_MAX_PERF_COUNTERS,
296 DRM_V3D_PARAM_SUPPORTS_SUPER_PAGES,
297};
298
299struct drm_v3d_get_param {
300 __u32 param;
301 __u32 pad;
302 __u64 value;
303};
304
305/**
306 * Returns the offset for the BO in the V3D address space for this DRM fd.
307 * This is the same value returned by drm_v3d_create_bo, if that was called
308 * from this DRM fd.
309 */
310struct drm_v3d_get_bo_offset {
311 __u32 handle;
312 __u32 offset;
313};
314
315struct drm_v3d_submit_tfu {
316 __u32 icfg;
317 __u32 iia;
318 __u32 iis;
319 __u32 ica;
320 __u32 iua;
321 __u32 ioa;
322 __u32 ios;
323 __u32 coef[4];
324 /* First handle is the output BO, following are other inputs.
325 * 0 for unused.
326 */
327 __u32 bo_handles[4];
328 /* sync object to block on before running the TFU job. Each TFU
329 * job will execute in the order submitted to its FD. Synchronization
330 * against rendering jobs requires using sync objects.
331 */
332 __u32 in_sync;
333 /* Sync object to signal when the TFU job is done. */
334 __u32 out_sync;
335
336 __u32 flags;
337
338 /* Pointer to an array of ioctl extensions*/
339 __u64 extensions;
340
341 struct {
342 __u32 ioc;
343 __u32 pad;
344 } v71;
345};
346
347/* Submits a compute shader for dispatch. This job will block on any
348 * previous compute shaders submitted on this fd, and any other
349 * synchronization must be performed with in_sync/out_sync.
350 */
351struct drm_v3d_submit_csd {
352 __u32 cfg[7];
353 __u32 coef[4];
354
355 /* Pointer to a u32 array of the BOs that are referenced by the job.
356 */
357 __u64 bo_handles;
358
359 /* Number of BO handles passed in (size is that times 4). */
360 __u32 bo_handle_count;
361
362 /* sync object to block on before running the CSD job. Each
363 * CSD job will execute in the order submitted to its FD.
364 * Synchronization against rendering/TFU jobs or CSD from
365 * other fds requires using sync objects.
366 */
367 __u32 in_sync;
368 /* Sync object to signal when the CSD job is done. */
369 __u32 out_sync;
370
371 /* ID of the perfmon to attach to this job. 0 means no perfmon. */
372 __u32 perfmon_id;
373
374 /* Pointer to an array of ioctl extensions*/
375 __u64 extensions;
376
377 __u32 flags;
378
379 __u32 pad;
380};
381
382/**
383 * struct drm_v3d_indirect_csd - ioctl extension for the CPU job to create an
384 * indirect CSD
385 *
386 * When an extension of DRM_V3D_EXT_ID_CPU_INDIRECT_CSD id is defined, it
387 * points to this extension to define a indirect CSD submission. It creates a
388 * CPU job linked to a CSD job. The CPU job waits for the indirect CSD
389 * dependencies and, once they are signaled, it updates the CSD job config
390 * before allowing the CSD job execution.
391 */
392struct drm_v3d_indirect_csd {
393 struct drm_v3d_extension base;
394
395 /* Indirect CSD */
396 struct drm_v3d_submit_csd submit;
397
398 /* Handle of the indirect BO, that should be also attached to the
399 * indirect CSD.
400 */
401 __u32 indirect;
402
403 /* Offset within the BO where the workgroup counts are stored */
404 __u32 offset;
405
406 /* Workgroups size */
407 __u32 wg_size;
408
409 /* Indices of the uniforms with the workgroup dispatch counts
410 * in the uniform stream. If the uniform rewrite is not needed,
411 * the offset must be 0xffffffff.
412 */
413 __u32 wg_uniform_offsets[3];
414};
415
416/**
417 * struct drm_v3d_timestamp_query - ioctl extension for the CPU job to calculate
418 * a timestamp query
419 *
420 * When an extension DRM_V3D_EXT_ID_TIMESTAMP_QUERY is defined, it points to
421 * this extension to define a timestamp query submission. This CPU job will
422 * calculate the timestamp query and update the query value within the
423 * timestamp BO. Moreover, it will signal the timestamp syncobj to indicate
424 * query availability.
425 */
426struct drm_v3d_timestamp_query {
427 struct drm_v3d_extension base;
428
429 /* Array of queries' offsets within the timestamp BO for their value */
430 __u64 offsets;
431
432 /* Array of timestamp's syncobjs to indicate its availability */
433 __u64 syncs;
434
435 /* Number of queries */
436 __u32 count;
437
438 /* mbz */
439 __u32 pad;
440};
441
442/**
443 * struct drm_v3d_reset_timestamp_query - ioctl extension for the CPU job to
444 * reset timestamp queries
445 *
446 * When an extension DRM_V3D_EXT_ID_CPU_RESET_TIMESTAMP_QUERY is defined, it
447 * points to this extension to define a reset timestamp submission. This CPU
448 * job will reset the timestamp queries based on value offset of the first
449 * query. Moreover, it will reset the timestamp syncobj to reset query
450 * availability.
451 */
452struct drm_v3d_reset_timestamp_query {
453 struct drm_v3d_extension base;
454
455 /* Array of timestamp's syncobjs to indicate its availability */
456 __u64 syncs;
457
458 /* Offset of the first query within the timestamp BO for its value */
459 __u32 offset;
460
461 /* Number of queries */
462 __u32 count;
463};
464
465/**
466 * struct drm_v3d_copy_timestamp_query - ioctl extension for the CPU job to copy
467 * query results to a buffer
468 *
469 * When an extension DRM_V3D_EXT_ID_CPU_COPY_TIMESTAMP_QUERY is defined, it
470 * points to this extension to define a copy timestamp query submission. This
471 * CPU job will copy the timestamp queries results to a BO with the offset
472 * and stride defined in the extension.
473 */
474struct drm_v3d_copy_timestamp_query {
475 struct drm_v3d_extension base;
476
477 /* Define if should write to buffer using 64 or 32 bits */
478 __u8 do_64bit;
479
480 /* Define if it can write to buffer even if the query is not available */
481 __u8 do_partial;
482
483 /* Define if it should write availability bit to buffer */
484 __u8 availability_bit;
485
486 /* mbz */
487 __u8 pad;
488
489 /* Offset of the buffer in the BO */
490 __u32 offset;
491
492 /* Stride of the buffer in the BO */
493 __u32 stride;
494
495 /* Number of queries */
496 __u32 count;
497
498 /* Array of queries' offsets within the timestamp BO for their value */
499 __u64 offsets;
500
501 /* Array of timestamp's syncobjs to indicate its availability */
502 __u64 syncs;
503};
504
505/**
506 * struct drm_v3d_reset_performance_query - ioctl extension for the CPU job to
507 * reset performance queries
508 *
509 * When an extension DRM_V3D_EXT_ID_CPU_RESET_PERFORMANCE_QUERY is defined, it
510 * points to this extension to define a reset performance submission. This CPU
511 * job will reset the performance queries by resetting the values of the
512 * performance monitors. Moreover, it will reset the syncobj to reset query
513 * availability.
514 */
515struct drm_v3d_reset_performance_query {
516 struct drm_v3d_extension base;
517
518 /* Array of performance queries's syncobjs to indicate its availability */
519 __u64 syncs;
520
521 /* Number of queries */
522 __u32 count;
523
524 /* Number of performance monitors */
525 __u32 nperfmons;
526
527 /* Array of u64 user-pointers that point to an array of kperfmon_ids */
528 __u64 kperfmon_ids;
529};
530
531/**
532 * struct drm_v3d_copy_performance_query - ioctl extension for the CPU job to copy
533 * performance query results to a buffer
534 *
535 * When an extension DRM_V3D_EXT_ID_CPU_COPY_PERFORMANCE_QUERY is defined, it
536 * points to this extension to define a copy performance query submission. This
537 * CPU job will copy the performance queries results to a BO with the offset
538 * and stride defined in the extension.
539 */
540struct drm_v3d_copy_performance_query {
541 struct drm_v3d_extension base;
542
543 /* Define if should write to buffer using 64 or 32 bits */
544 __u8 do_64bit;
545
546 /* Define if it can write to buffer even if the query is not available */
547 __u8 do_partial;
548
549 /* Define if it should write availability bit to buffer */
550 __u8 availability_bit;
551
552 /* mbz */
553 __u8 pad;
554
555 /* Offset of the buffer in the BO */
556 __u32 offset;
557
558 /* Stride of the buffer in the BO */
559 __u32 stride;
560
561 /* Number of performance monitors */
562 __u32 nperfmons;
563
564 /* Number of performance counters related to this query pool */
565 __u32 ncounters;
566
567 /* Number of queries */
568 __u32 count;
569
570 /* Array of performance queries's syncobjs to indicate its availability */
571 __u64 syncs;
572
573 /* Array of u64 user-pointers that point to an array of kperfmon_ids */
574 __u64 kperfmon_ids;
575};
576
577struct drm_v3d_submit_cpu {
578 /* Pointer to a u32 array of the BOs that are referenced by the job.
579 *
580 * For DRM_V3D_EXT_ID_CPU_INDIRECT_CSD, it must contain only one BO,
581 * that contains the workgroup counts.
582 *
583 * For DRM_V3D_EXT_ID_TIMESTAMP_QUERY, it must contain only one BO,
584 * that will contain the timestamp.
585 *
586 * For DRM_V3D_EXT_ID_CPU_RESET_TIMESTAMP_QUERY, it must contain only
587 * one BO, that contains the timestamp.
588 *
589 * For DRM_V3D_EXT_ID_CPU_COPY_TIMESTAMP_QUERY, it must contain two
590 * BOs. The first is the BO where the timestamp queries will be written
591 * to. The second is the BO that contains the timestamp.
592 *
593 * For DRM_V3D_EXT_ID_CPU_RESET_PERFORMANCE_QUERY, it must contain no
594 * BOs.
595 *
596 * For DRM_V3D_EXT_ID_CPU_COPY_PERFORMANCE_QUERY, it must contain one
597 * BO, where the performance queries will be written.
598 */
599 __u64 bo_handles;
600
601 /* Number of BO handles passed in (size is that times 4). */
602 __u32 bo_handle_count;
603
604 __u32 flags;
605
606 /* Pointer to an array of ioctl extensions*/
607 __u64 extensions;
608};
609
610/* The performance counters index represented by this enum are deprecated and
611 * must no longer be used. These counters are only valid for V3D 4.2.
612 *
613 * In order to check for performance counter information,
614 * use DRM_IOCTL_V3D_PERFMON_GET_COUNTER.
615 *
616 * Don't use V3D_PERFCNT_NUM to retrieve the maximum number of performance
617 * counters. You should use DRM_IOCTL_V3D_GET_PARAM with the following
618 * parameter: DRM_V3D_PARAM_MAX_PERF_COUNTERS.
619 */
620enum {
621 V3D_PERFCNT_FEP_VALID_PRIMTS_NO_PIXELS,
622 V3D_PERFCNT_FEP_VALID_PRIMS,
623 V3D_PERFCNT_FEP_EZ_NFCLIP_QUADS,
624 V3D_PERFCNT_FEP_VALID_QUADS,
625 V3D_PERFCNT_TLB_QUADS_STENCIL_FAIL,
626 V3D_PERFCNT_TLB_QUADS_STENCILZ_FAIL,
627 V3D_PERFCNT_TLB_QUADS_STENCILZ_PASS,
628 V3D_PERFCNT_TLB_QUADS_ZERO_COV,
629 V3D_PERFCNT_TLB_QUADS_NONZERO_COV,
630 V3D_PERFCNT_TLB_QUADS_WRITTEN,
631 V3D_PERFCNT_PTB_PRIM_VIEWPOINT_DISCARD,
632 V3D_PERFCNT_PTB_PRIM_CLIP,
633 V3D_PERFCNT_PTB_PRIM_REV,
634 V3D_PERFCNT_QPU_IDLE_CYCLES,
635 V3D_PERFCNT_QPU_ACTIVE_CYCLES_VERTEX_COORD_USER,
636 V3D_PERFCNT_QPU_ACTIVE_CYCLES_FRAG,
637 V3D_PERFCNT_QPU_CYCLES_VALID_INSTR,
638 V3D_PERFCNT_QPU_CYCLES_TMU_STALL,
639 V3D_PERFCNT_QPU_CYCLES_SCOREBOARD_STALL,
640 V3D_PERFCNT_QPU_CYCLES_VARYINGS_STALL,
641 V3D_PERFCNT_QPU_IC_HIT,
642 V3D_PERFCNT_QPU_IC_MISS,
643 V3D_PERFCNT_QPU_UC_HIT,
644 V3D_PERFCNT_QPU_UC_MISS,
645 V3D_PERFCNT_TMU_TCACHE_ACCESS,
646 V3D_PERFCNT_TMU_TCACHE_MISS,
647 V3D_PERFCNT_VPM_VDW_STALL,
648 V3D_PERFCNT_VPM_VCD_STALL,
649 V3D_PERFCNT_BIN_ACTIVE,
650 V3D_PERFCNT_RDR_ACTIVE,
651 V3D_PERFCNT_L2T_HITS,
652 V3D_PERFCNT_L2T_MISSES,
653 V3D_PERFCNT_CYCLE_COUNT,
654 V3D_PERFCNT_QPU_CYCLES_STALLED_VERTEX_COORD_USER,
655 V3D_PERFCNT_QPU_CYCLES_STALLED_FRAGMENT,
656 V3D_PERFCNT_PTB_PRIMS_BINNED,
657 V3D_PERFCNT_AXI_WRITES_WATCH_0,
658 V3D_PERFCNT_AXI_READS_WATCH_0,
659 V3D_PERFCNT_AXI_WRITE_STALLS_WATCH_0,
660 V3D_PERFCNT_AXI_READ_STALLS_WATCH_0,
661 V3D_PERFCNT_AXI_WRITE_BYTES_WATCH_0,
662 V3D_PERFCNT_AXI_READ_BYTES_WATCH_0,
663 V3D_PERFCNT_AXI_WRITES_WATCH_1,
664 V3D_PERFCNT_AXI_READS_WATCH_1,
665 V3D_PERFCNT_AXI_WRITE_STALLS_WATCH_1,
666 V3D_PERFCNT_AXI_READ_STALLS_WATCH_1,
667 V3D_PERFCNT_AXI_WRITE_BYTES_WATCH_1,
668 V3D_PERFCNT_AXI_READ_BYTES_WATCH_1,
669 V3D_PERFCNT_TLB_PARTIAL_QUADS,
670 V3D_PERFCNT_TMU_CONFIG_ACCESSES,
671 V3D_PERFCNT_L2T_NO_ID_STALL,
672 V3D_PERFCNT_L2T_COM_QUE_STALL,
673 V3D_PERFCNT_L2T_TMU_WRITES,
674 V3D_PERFCNT_TMU_ACTIVE_CYCLES,
675 V3D_PERFCNT_TMU_STALLED_CYCLES,
676 V3D_PERFCNT_CLE_ACTIVE,
677 V3D_PERFCNT_L2T_TMU_READS,
678 V3D_PERFCNT_L2T_CLE_READS,
679 V3D_PERFCNT_L2T_VCD_READS,
680 V3D_PERFCNT_L2T_TMUCFG_READS,
681 V3D_PERFCNT_L2T_SLC0_READS,
682 V3D_PERFCNT_L2T_SLC1_READS,
683 V3D_PERFCNT_L2T_SLC2_READS,
684 V3D_PERFCNT_L2T_TMU_W_MISSES,
685 V3D_PERFCNT_L2T_TMU_R_MISSES,
686 V3D_PERFCNT_L2T_CLE_MISSES,
687 V3D_PERFCNT_L2T_VCD_MISSES,
688 V3D_PERFCNT_L2T_TMUCFG_MISSES,
689 V3D_PERFCNT_L2T_SLC0_MISSES,
690 V3D_PERFCNT_L2T_SLC1_MISSES,
691 V3D_PERFCNT_L2T_SLC2_MISSES,
692 V3D_PERFCNT_CORE_MEM_WRITES,
693 V3D_PERFCNT_L2T_MEM_WRITES,
694 V3D_PERFCNT_PTB_MEM_WRITES,
695 V3D_PERFCNT_TLB_MEM_WRITES,
696 V3D_PERFCNT_CORE_MEM_READS,
697 V3D_PERFCNT_L2T_MEM_READS,
698 V3D_PERFCNT_PTB_MEM_READS,
699 V3D_PERFCNT_PSE_MEM_READS,
700 V3D_PERFCNT_TLB_MEM_READS,
701 V3D_PERFCNT_GMP_MEM_READS,
702 V3D_PERFCNT_PTB_W_MEM_WORDS,
703 V3D_PERFCNT_TLB_W_MEM_WORDS,
704 V3D_PERFCNT_PSE_R_MEM_WORDS,
705 V3D_PERFCNT_TLB_R_MEM_WORDS,
706 V3D_PERFCNT_TMU_MRU_HITS,
707 V3D_PERFCNT_COMPUTE_ACTIVE,
708 V3D_PERFCNT_NUM,
709};
710
711#define DRM_V3D_MAX_PERF_COUNTERS 32
712
713struct drm_v3d_perfmon_create {
714 __u32 id;
715 __u32 ncounters;
716 __u8 counters[DRM_V3D_MAX_PERF_COUNTERS];
717};
718
719struct drm_v3d_perfmon_destroy {
720 __u32 id;
721};
722
723/*
724 * Returns the values of the performance counters tracked by this
725 * perfmon (as an array of ncounters u64 values).
726 *
727 * No implicit synchronization is performed, so the user has to
728 * guarantee that any jobs using this perfmon have already been
729 * completed (probably by blocking on the seqno returned by the
730 * last exec that used the perfmon).
731 */
732struct drm_v3d_perfmon_get_values {
733 __u32 id;
734 __u32 pad;
735 __u64 values_ptr;
736};
737
738#define DRM_V3D_PERFCNT_MAX_NAME 64
739#define DRM_V3D_PERFCNT_MAX_CATEGORY 32
740#define DRM_V3D_PERFCNT_MAX_DESCRIPTION 256
741
742/**
743 * struct drm_v3d_perfmon_get_counter - ioctl to get the description of a
744 * performance counter
745 *
746 * As userspace needs to retrieve information about the performance counters
747 * available, this IOCTL allows users to get information about a performance
748 * counter (name, category and description).
749 */
750struct drm_v3d_perfmon_get_counter {
751 /*
752 * Counter ID
753 *
754 * Must be smaller than the maximum number of performance counters, which
755 * can be retrieve through DRM_V3D_PARAM_MAX_PERF_COUNTERS.
756 */
757 __u8 counter;
758
759 /* Name of the counter */
760 __u8 name[DRM_V3D_PERFCNT_MAX_NAME];
761
762 /* Category of the counter */
763 __u8 category[DRM_V3D_PERFCNT_MAX_CATEGORY];
764
765 /* Description of the counter */
766 __u8 description[DRM_V3D_PERFCNT_MAX_DESCRIPTION];
767
768 /* mbz */
769 __u8 reserved[7];
770};
771
772#define DRM_V3D_PERFMON_CLEAR_GLOBAL 0x0001
773
774/**
775 * struct drm_v3d_perfmon_set_global - ioctl to define a global performance
776 * monitor
777 *
778 * The global performance monitor will be used for all jobs. If a global
779 * performance monitor is defined, jobs with a self-defined performance
780 * monitor won't be allowed.
781 */
782struct drm_v3d_perfmon_set_global {
783 __u32 flags;
784 __u32 id;
785};
786
787#if defined(__cplusplus)
788}
789#endif
790
791#endif /* _V3D_DRM_H_ */