master
1/* $NetBSD: pmap.h,v 1.57 2022/11/03 09:04:56 skrll Exp $ */
2
3/*-
4 * Copyright (c) 2014 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Matt Thomas of 3am Software Foundry.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#ifndef _AARCH64_PMAP_H_
33#define _AARCH64_PMAP_H_
34
35#ifdef __aarch64__
36
37#ifdef _KERNEL
38#ifdef _KERNEL_OPT
39#include "opt_kasan.h"
40#include "opt_pmap.h"
41#endif
42
43#include <sys/types.h>
44#include <sys/pool.h>
45#include <sys/queue.h>
46
47#include <uvm/uvm_pglist.h>
48
49#include <aarch64/armreg.h>
50#include <aarch64/pte.h>
51
52#define PMAP_TLB_MAX 1
53#if PMAP_TLB_MAX > 1
54#define PMAP_TLB_NEED_SHOOTDOWN 1
55#endif
56
57#define PMAP_TLB_FLUSH_ASID_ON_RESET true
58
59/* Maximum number of ASIDs. Some CPUs have less.*/
60#define PMAP_TLB_NUM_PIDS 65536
61#define PMAP_TLB_BITMAP_LENGTH PMAP_TLB_NUM_PIDS
62#define cpu_set_tlb_info(ci, ti) ((void)((ci)->ci_tlb_info = (ti)))
63#if PMAP_TLB_MAX > 1
64#define cpu_tlb_info(ci) ((ci)->ci_tlb_info)
65#else
66#define cpu_tlb_info(ci) (&pmap_tlb0_info)
67#endif
68
69static inline tlb_asid_t
70pmap_md_tlb_asid_max(void)
71{
72 switch (__SHIFTOUT(reg_id_aa64mmfr0_el1_read(), ID_AA64MMFR0_EL1_ASIDBITS)) {
73 case ID_AA64MMFR0_EL1_ASIDBITS_8BIT:
74 return (1U << 8) - 1;
75 case ID_AA64MMFR0_EL1_ASIDBITS_16BIT:
76 return (1U << 16) - 1;
77 default:
78 return 0;
79 }
80}
81
82#include <uvm/pmap/tlb.h>
83#include <uvm/pmap/pmap_tlb.h>
84
85#define KERNEL_PID 0 /* The kernel uses ASID 0 */
86
87
88/* memory attributes are configured MAIR_EL1 in locore */
89#define LX_BLKPAG_ATTR_NORMAL_WB __SHIFTIN(0, LX_BLKPAG_ATTR_INDX)
90#define LX_BLKPAG_ATTR_NORMAL_NC __SHIFTIN(1, LX_BLKPAG_ATTR_INDX)
91#define LX_BLKPAG_ATTR_NORMAL_WT __SHIFTIN(2, LX_BLKPAG_ATTR_INDX)
92#define LX_BLKPAG_ATTR_DEVICE_MEM __SHIFTIN(3, LX_BLKPAG_ATTR_INDX)
93#define LX_BLKPAG_ATTR_DEVICE_MEM_NP __SHIFTIN(4, LX_BLKPAG_ATTR_INDX)
94#define LX_BLKPAG_ATTR_MASK LX_BLKPAG_ATTR_INDX
95
96#define lxpde_pa(pde) ((paddr_t)((pde) & LX_TBL_PA))
97#define lxpde_valid(pde) (((pde) & LX_VALID) == LX_VALID)
98#define l0pde_pa(pde) lxpde_pa(pde)
99#define l0pde_index(v) (((vaddr_t)(v) & L0_ADDR_BITS) >> L0_SHIFT)
100#define l0pde_valid(pde) lxpde_valid(pde)
101/* l0pte always contains table entries */
102
103#define l1pde_pa(pde) lxpde_pa(pde)
104#define l1pde_index(v) (((vaddr_t)(v) & L1_ADDR_BITS) >> L1_SHIFT)
105#define l1pde_valid(pde) lxpde_valid(pde)
106#define l1pde_is_block(pde) (((pde) & LX_TYPE) == LX_TYPE_BLK)
107#define l1pde_is_table(pde) (((pde) & LX_TYPE) == LX_TYPE_TBL)
108
109#define l2pde_pa(pde) lxpde_pa(pde)
110#define l2pde_index(v) (((vaddr_t)(v) & L2_ADDR_BITS) >> L2_SHIFT)
111#define l2pde_valid(pde) lxpde_valid(pde)
112#define l2pde_is_block(pde) (((pde) & LX_TYPE) == LX_TYPE_BLK)
113#define l2pde_is_table(pde) (((pde) & LX_TYPE) == LX_TYPE_TBL)
114
115#define l3pte_pa(pde) lxpde_pa(pde)
116#define l3pte_executable(pde,user) \
117 (((pde) & ((user) ? LX_BLKPAG_UXN : LX_BLKPAG_PXN)) == 0)
118#define l3pte_readable(pde) ((pde) & LX_BLKPAG_AF)
119#define l3pte_writable(pde) \
120 (((pde) & (LX_BLKPAG_AF | LX_BLKPAG_AP)) == (LX_BLKPAG_AF | LX_BLKPAG_AP_RW))
121#define l3pte_index(v) (((vaddr_t)(v) & L3_ADDR_BITS) >> L3_SHIFT)
122#define l3pte_valid(pde) lxpde_valid(pde)
123#define l3pte_is_page(pde) (((pde) & LX_TYPE) == L3_TYPE_PAG)
124
125pd_entry_t *pmap_l0table(struct pmap *);
126void pmap_bootstrap(vaddr_t, vaddr_t);
127bool pmap_fault_fixup(struct pmap *, vaddr_t, vm_prot_t, bool user);
128
129bool pmap_extract_coherency(pmap_t, vaddr_t, paddr_t *, bool *);
130
131
132/* change attribute of kernel segment */
133static inline pt_entry_t
134pmap_kvattr(pt_entry_t *ptep, vm_prot_t prot)
135{
136 pt_entry_t pte = *ptep;
137 const pt_entry_t opte = pte;
138
139 pte &= ~(LX_BLKPAG_AF | LX_BLKPAG_AP);
140 switch (prot & (VM_PROT_READ | VM_PROT_WRITE)) {
141 case 0:
142 break;
143 case VM_PROT_READ:
144 pte |= LX_BLKPAG_AF | LX_BLKPAG_AP_RO;
145 break;
146 case VM_PROT_WRITE:
147 case VM_PROT_READ | VM_PROT_WRITE:
148 pte |= LX_BLKPAG_AF | LX_BLKPAG_AP_RW;
149 break;
150 }
151
152 if ((prot & VM_PROT_EXECUTE) == 0) {
153 pte |= LX_BLKPAG_PXN;
154 } else {
155 pte |= LX_BLKPAG_AF;
156 pte &= ~LX_BLKPAG_PXN;
157 }
158
159 *ptep = pte;
160
161 return opte;
162}
163
164/* devmap */
165struct pmap_devmap {
166 vaddr_t pd_va; /* virtual address */
167 paddr_t pd_pa; /* physical address */
168 psize_t pd_size; /* size of region */
169 vm_prot_t pd_prot; /* protection code */
170 u_int pd_flags; /* flags for pmap_kenter_pa() */
171};
172
173void pmap_devmap_register(const struct pmap_devmap *);
174void pmap_devmap_bootstrap(vaddr_t, const struct pmap_devmap *);
175const struct pmap_devmap *pmap_devmap_find_pa(paddr_t, psize_t);
176const struct pmap_devmap *pmap_devmap_find_va(vaddr_t, vsize_t);
177vaddr_t pmap_devmap_phystov(paddr_t);
178paddr_t pmap_devmap_vtophys(paddr_t);
179
180#define L1_TRUNC_BLOCK(x) ((x) & L1_FRAME)
181#define L1_ROUND_BLOCK(x) L1_TRUNC_BLOCK((x) + L1_SIZE - 1)
182#define L2_TRUNC_BLOCK(x) ((x) & L2_FRAME)
183#define L2_ROUND_BLOCK(x) L2_TRUNC_BLOCK((x) + L2_SIZE - 1)
184#define L3_TRUNC_BLOCK(x) ((x) & L3_FRAME)
185#define L3_ROUND_BLOCK(x) L3_TRUNC_BLOCK((x) + L3_SIZE - 1)
186
187#define DEVMAP_ALIGN(x) L3_TRUNC_BLOCK((x))
188#define DEVMAP_SIZE(x) L3_ROUND_BLOCK((x))
189
190#define DEVMAP_ENTRY(va, pa, sz) \
191 { \
192 .pd_va = DEVMAP_ALIGN(va), \
193 .pd_pa = DEVMAP_ALIGN(pa), \
194 .pd_size = DEVMAP_SIZE(sz), \
195 .pd_prot = VM_PROT_READ | VM_PROT_WRITE, \
196 .pd_flags = PMAP_DEV \
197 }
198#define DEVMAP_ENTRY_END { 0 }
199
200/* Hooks for the pool allocator */
201paddr_t vtophys(vaddr_t);
202
203/* mmap cookie and flags */
204#define AARCH64_MMAP_FLAG_SHIFT (64 - PGSHIFT)
205#define AARCH64_MMAP_FLAG_MASK 0xf
206#define AARCH64_MMAP_WRITEBACK 0UL
207#define AARCH64_MMAP_NOCACHE 1UL
208#define AARCH64_MMAP_WRITECOMBINE 2UL
209#define AARCH64_MMAP_DEVICE 3UL
210
211#define ARM_MMAP_MASK __BITS(63, AARCH64_MMAP_FLAG_SHIFT)
212#define ARM_MMAP_WRITECOMBINE __SHIFTIN(AARCH64_MMAP_WRITECOMBINE, ARM_MMAP_MASK)
213#define ARM_MMAP_WRITEBACK __SHIFTIN(AARCH64_MMAP_WRITEBACK, ARM_MMAP_MASK)
214#define ARM_MMAP_NOCACHE __SHIFTIN(AARCH64_MMAP_NOCACHE, ARM_MMAP_MASK)
215#define ARM_MMAP_DEVICE __SHIFTIN(AARCH64_MMAP_DEVICE, ARM_MMAP_MASK)
216
217#define PMAP_PTE 0x10000000 /* kenter_pa */
218#define PMAP_DEV 0x20000000 /* kenter_pa */
219#define PMAP_DEV_NP 0x40000000 /* kenter_pa */
220#define PMAP_DEV_MASK (PMAP_DEV | PMAP_DEV_NP)
221
222static inline u_int
223aarch64_mmap_flags(paddr_t mdpgno)
224{
225 u_int nflag, pflag;
226
227 /*
228 * aarch64 arch has 5 memory attributes defined:
229 *
230 * WriteBack - write back cache
231 * WriteThru - write through cache
232 * NoCache - no cache
233 * Device(nGnRE) - no Gathering, no Reordering, Early write ack
234 * Device(nGnRnE) - no Gathering, no Reordering, no Early write ack
235 *
236 * but pmap has PMAP_{NOCACHE,WRITE_COMBINE,WRITE_BACK} flags.
237 */
238
239 nflag = (mdpgno >> AARCH64_MMAP_FLAG_SHIFT) & AARCH64_MMAP_FLAG_MASK;
240 switch (nflag) {
241 case AARCH64_MMAP_DEVICE:
242 pflag = PMAP_DEV;
243 break;
244 case AARCH64_MMAP_WRITECOMBINE:
245 pflag = PMAP_WRITE_COMBINE;
246 break;
247 case AARCH64_MMAP_WRITEBACK:
248 pflag = PMAP_WRITE_BACK;
249 break;
250 case AARCH64_MMAP_NOCACHE:
251 default:
252 pflag = PMAP_NOCACHE;
253 break;
254 }
255 return pflag;
256}
257
258#define pmap_phys_address(pa) aarch64_ptob((pa))
259#define pmap_mmap_flags(ppn) aarch64_mmap_flags((ppn))
260
261void pmap_bootstrap(vaddr_t, vaddr_t);
262bool pmap_fault_fixup(struct pmap *, vaddr_t, vm_prot_t, bool user);
263
264pd_entry_t *pmapboot_pagealloc(void);
265void pmapboot_enter(vaddr_t, paddr_t, psize_t, psize_t, pt_entry_t,
266 void (*pr)(const char *, ...) __printflike(1, 2));
267void pmapboot_enter_range(vaddr_t, paddr_t, psize_t, pt_entry_t,
268 void (*)(const char *, ...) __printflike(1, 2));
269int pmapboot_protect(vaddr_t, vaddr_t, vm_prot_t);
270
271#if defined(DDB)
272void pmap_db_pte_print(pt_entry_t, int, void (*)(const char *, ...) __printflike(1, 2));
273void pmap_db_pteinfo(vaddr_t, void (*)(const char *, ...) __printflike(1, 2));
274void pmap_db_ttbrdump(bool, vaddr_t, void (*)(const char *, ...) __printflike(1, 2));
275#endif
276
277#define LX_BLKPAG_OS_WIRED LX_BLKPAG_OS_2
278#define LX_BLKPAG_OS_BOOT LX_BLKPAG_OS_3
279
280#define PMAP_PTE_OS2 "wired"
281#define PMAP_PTE_OS3 "boot"
282
283#if defined(PMAP_MI)
284#include <aarch64/pmap_machdep.h>
285#else
286
287#define PMAP_NEED_PROCWR
288#define PMAP_GROWKERNEL
289#define PMAP_STEAL_MEMORY
290
291#define __HAVE_VM_PAGE_MD
292#define __HAVE_PMAP_PV_TRACK 1
293
294struct pmap {
295 kmutex_t pm_lock;
296 struct pool *pm_pvpool;
297 pd_entry_t *pm_l0table; /* L0 table: 512G*512 */
298 paddr_t pm_l0table_pa;
299
300 LIST_HEAD(, vm_page) pm_vmlist; /* for L[0123] tables */
301 LIST_HEAD(, pv_entry) pm_pvlist; /* all pv of this process */
302
303 struct pmap_statistics pm_stats;
304 unsigned int pm_refcnt;
305 unsigned int pm_idlepdp;
306
307 kcpuset_t *pm_onproc;
308 kcpuset_t *pm_active;
309
310 struct pmap_asid_info pm_pai[PMAP_TLB_MAX];
311 bool pm_activated;
312};
313
314static inline paddr_t
315pmap_l0pa(struct pmap *pm)
316{
317 return pm->pm_l0table_pa;
318}
319
320
321/*
322 * should be kept <=32 bytes sized to reduce memory consumption & cache misses,
323 * but it doesn't...
324 */
325struct pv_entry {
326 struct pv_entry *pv_next;
327 struct pmap *pv_pmap;
328 vaddr_t pv_va; /* for embedded entry (pp_pv) also includes flags */
329 void *pv_ptep; /* pointer for fast pte lookup */
330 LIST_ENTRY(pv_entry) pv_proc; /* belonging to the process */
331};
332
333struct pmap_page {
334 kmutex_t pp_pvlock;
335 struct pv_entry pp_pv;
336};
337
338/* try to keep vm_page at or under 128 bytes to reduce cache misses */
339struct vm_page_md {
340 struct pmap_page mdpg_pp;
341};
342/* for page descriptor page only */
343#define mdpg_ptep_parent mdpg_pp.pp_pv.pv_ptep
344
345#define VM_MDPAGE_INIT(pg) \
346 do { \
347 PMAP_PAGE_INIT(&(pg)->mdpage.mdpg_pp); \
348 } while (/*CONSTCOND*/ 0)
349
350#define PMAP_PAGE_INIT(pp) \
351 do { \
352 mutex_init(&(pp)->pp_pvlock, MUTEX_NODEBUG, IPL_NONE); \
353 (pp)->pp_pv.pv_next = NULL; \
354 (pp)->pp_pv.pv_pmap = NULL; \
355 (pp)->pp_pv.pv_va = 0; \
356 (pp)->pp_pv.pv_ptep = NULL; \
357 } while (/*CONSTCOND*/ 0)
358
359/* saved permission bit for referenced/modified emulation */
360#define LX_BLKPAG_OS_READ LX_BLKPAG_OS_0
361#define LX_BLKPAG_OS_WRITE LX_BLKPAG_OS_1
362#define LX_BLKPAG_OS_RWMASK (LX_BLKPAG_OS_WRITE | LX_BLKPAG_OS_READ)
363
364#define PMAP_PTE_OS0 "read"
365#define PMAP_PTE_OS1 "write"
366
367#define VTOPHYS_FAILED ((paddr_t)-1L) /* POOL_PADDR_INVALID */
368#define POOL_VTOPHYS(va) vtophys((vaddr_t) (va))
369
370#ifndef KASAN
371#define PMAP_MAP_POOLPAGE(pa) AARCH64_PA_TO_KVA(pa)
372#define PMAP_UNMAP_POOLPAGE(va) AARCH64_KVA_TO_PA(va)
373
374#define PMAP_DIRECT
375static __inline int
376pmap_direct_process(paddr_t pa, voff_t pgoff, size_t len,
377 int (*process)(void *, size_t, void *), void *arg)
378{
379 vaddr_t va = AARCH64_PA_TO_KVA(pa);
380
381 return process((void *)(va + pgoff), len, arg);
382}
383#endif
384
385/* l3pte contains always page entries */
386static inline uint64_t
387pte_value(pt_entry_t pte)
388{
389 return pte;
390}
391
392static inline bool
393pte_valid_p(pt_entry_t pte)
394{
395 return l3pte_valid(pte);
396}
397
398pt_entry_t *kvtopte(vaddr_t);
399
400#define pmap_update(pmap) ((void)0)
401#define pmap_copy(dp,sp,d,l,s) ((void)0)
402#define pmap_wired_count(pmap) ((pmap)->pm_stats.wired_count)
403#define pmap_resident_count(pmap) ((pmap)->pm_stats.resident_count)
404
405struct pmap *
406 pmap_efirt(void);
407void pmap_activate_efirt(void);
408void pmap_deactivate_efirt(void);
409
410void pmap_procwr(struct proc *, vaddr_t, int);
411void pmap_icache_sync_range(pmap_t, vaddr_t, vaddr_t);
412
413void pmap_pv_init(void);
414void pmap_pv_track(paddr_t, psize_t);
415void pmap_pv_untrack(paddr_t, psize_t);
416void pmap_pv_protect(paddr_t, vm_prot_t);
417
418#define PMAP_MAPSIZE1 L2_SIZE
419
420/* for ddb */
421void pmap_db_pmap_print(struct pmap *, void (*)(const char *, ...) __printflike(1, 2));
422void pmap_db_mdpg_print(struct vm_page *, void (*)(const char *, ...) __printflike(1, 2));
423
424#endif /* !PMAP_MI */
425
426#endif /* _KERNEL */
427
428#elif defined(__arm__)
429
430#include <arm/pmap.h>
431
432#endif /* __arm__/__aarch64__ */
433
434#endif /* !_AARCH64_PMAP_ */