1/*-
  2 * Copyright (c) 2014 Andrew Turner
  3 * Copyright (c) 2014-2015 The FreeBSD Foundation
  4 * All rights reserved.
  5 *
  6 * This software was developed by Andrew Turner under
  7 * sponsorship from the FreeBSD Foundation.
  8 *
  9 * Redistribution and use in source and binary forms, with or without
 10 * modification, are permitted provided that the following conditions
 11 * are met:
 12 * 1. Redistributions of source code must retain the above copyright
 13 *    notice, this list of conditions and the following disclaimer.
 14 * 2. Redistributions in binary form must reproduce the above copyright
 15 *    notice, this list of conditions and the following disclaimer in the
 16 *    documentation and/or other materials provided with the distribution.
 17 *
 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 21 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 28 * SUCH DAMAGE.
 29 */
 30
 31#ifdef __arm__
 32#include <arm/pte.h>
 33#else /* !__arm__ */
 34
 35#ifndef _MACHINE_PTE_H_
 36#define	_MACHINE_PTE_H_
 37
 38#ifndef LOCORE
 39typedef	uint64_t	pd_entry_t;		/* page directory entry */
 40typedef	uint64_t	pt_entry_t;		/* page table entry */
 41#endif
 42
 43/* Table attributes */
 44#define	TATTR_MASK		UINT64_C(0xfff8000000000000)
 45#define	TATTR_AP_TABLE_MASK	(3UL << 61)
 46#define	TATTR_AP_TABLE_RO	(2UL << 61)
 47#define	TATTR_AP_TABLE_NO_EL0	(1UL << 61)
 48#define	TATTR_UXN_TABLE		(1UL << 60)
 49#define	TATTR_PXN_TABLE		(1UL << 59)
 50/* Bits 58:51 are ignored */
 51
 52/* Block and Page attributes */
 53#define	ATTR_MASK_H		UINT64_C(0xfffc000000000000)
 54#define	ATTR_MASK_L		UINT64_C(0x0000000000000fff)
 55#define	ATTR_MASK		(ATTR_MASK_H | ATTR_MASK_L)
 56
 57#define BASE_MASK		~ATTR_MASK
 58#define BASE_ADDR(x)		((x) & BASE_MASK)
 59
 60#define PTE_TO_PHYS(pte)	BASE_ADDR(pte)
 61/* Convert a phys addr to the output address field of a PTE */
 62#define PHYS_TO_PTE(pa)		(pa)
 63
 64/* Bits 58:55 are reserved for software */
 65#define	ATTR_SW_UNUSED1		(1UL << 58)
 66#define	ATTR_SW_NO_PROMOTE	(1UL << 57)
 67#define	ATTR_SW_MANAGED		(1UL << 56)
 68#define	ATTR_SW_WIRED		(1UL << 55)
 69
 70#define	ATTR_S1_UXN		(1UL << 54)
 71#define	ATTR_S1_PXN		(1UL << 53)
 72#define	ATTR_S1_XN		(ATTR_S1_PXN | ATTR_S1_UXN)
 73
 74#define	ATTR_S2_XN(x)		((x) << 53)
 75#define	 ATTR_S2_XN_MASK	ATTR_S2_XN(3UL)
 76#define	 ATTR_S2_XN_NONE	0UL	/* Allow execution at EL0 & EL1 */
 77#define	 ATTR_S2_XN_EL1		1UL	/* Allow execution at EL0 */
 78#define	 ATTR_S2_XN_ALL		2UL	/* No execution */
 79#define	 ATTR_S2_XN_EL0		3UL	/* Allow execution at EL1 */
 80
 81#define	ATTR_CONTIGUOUS		(1UL << 52)
 82#define	ATTR_DBM		(1UL << 51)
 83#define	ATTR_S1_nG		(1 << 11)
 84#define	ATTR_AF			(1 << 10)
 85#define	ATTR_SH(x)		((x) << 8)
 86#define	 ATTR_SH_MASK		ATTR_SH(3)
 87#define	 ATTR_SH_NS		0		/* Non-shareable */
 88#define	 ATTR_SH_OS		2		/* Outer-shareable */
 89#define	 ATTR_SH_IS		3		/* Inner-shareable */
 90
 91#define	ATTR_S1_AP_RW_BIT	(1 << 7)
 92#define	ATTR_S1_AP(x)		((x) << 6)
 93#define	 ATTR_S1_AP_MASK	ATTR_S1_AP(3)
 94#define	 ATTR_S1_AP_RW		(0 << 1)
 95#define	 ATTR_S1_AP_RO		(1 << 1)
 96#define	 ATTR_S1_AP_USER	(1 << 0)
 97#define	ATTR_S1_NS		(1 << 5)
 98#define	ATTR_S1_IDX(x)		((x) << 2)
 99#define	ATTR_S1_IDX_MASK	(7 << 2)
100
101#define	ATTR_S2_S2AP(x)		((x) << 6)
102#define	 ATTR_S2_S2AP_MASK	3
103#define	 ATTR_S2_S2AP_READ	1
104#define	 ATTR_S2_S2AP_WRITE	2
105
106#define	ATTR_S2_MEMATTR(x)		((x) << 2)
107#define	 ATTR_S2_MEMATTR_MASK		ATTR_S2_MEMATTR(0xf)
108#define	 ATTR_S2_MEMATTR_DEVICE_nGnRnE	0x0
109#define	 ATTR_S2_MEMATTR_NC		0xf
110#define	 ATTR_S2_MEMATTR_WT		0xa
111#define	 ATTR_S2_MEMATTR_WB		0xf
112
113#define	ATTR_DEFAULT	(ATTR_AF | ATTR_SH(ATTR_SH_IS))
114
115#define	ATTR_DESCR_MASK		3
116#define	ATTR_DESCR_VALID	1
117#define	ATTR_DESCR_TYPE_MASK	2
118#define	ATTR_DESCR_TYPE_TABLE	2
119#define	ATTR_DESCR_TYPE_PAGE	2
120#define	ATTR_DESCR_TYPE_BLOCK	0
121
122#if PAGE_SIZE == PAGE_SIZE_4K
123#define	L0_SHIFT	39
124#define	L1_SHIFT	30
125#define	L2_SHIFT	21
126#define	L3_SHIFT	12
127#elif PAGE_SIZE == PAGE_SIZE_16K
128#define	L0_SHIFT	47
129#define	L1_SHIFT	36
130#define	L2_SHIFT	25
131#define	L3_SHIFT	14
132#else
133#error Unsupported page size
134#endif
135
136/* Level 0 table, 512GiB/128TiB per entry */
137#define	L0_SIZE		(UINT64_C(1) << L0_SHIFT)
138#define	L0_OFFSET	(L0_SIZE - 1ul)
139#define	L0_INVAL	0x0 /* An invalid address */
140	/* 0x1 Level 0 doesn't support block translation */
141	/* 0x2 also marks an invalid address */
142#define	L0_TABLE	0x3 /* A next-level table */
143
144/* Level 1 table, 1GiB/64GiB per entry */
145#define	L1_SIZE 	(UINT64_C(1) << L1_SHIFT)
146#define	L1_OFFSET 	(L1_SIZE - 1)
147#define	L1_INVAL	L0_INVAL
148#define	L1_BLOCK	0x1
149#define	L1_TABLE	L0_TABLE
150
151/* Level 2 table, 2MiB/32MiB per entry */
152#define	L2_SIZE 	(UINT64_C(1) << L2_SHIFT)
153#define	L2_OFFSET 	(L2_SIZE - 1)
154#define	L2_INVAL	L1_INVAL
155#define	L2_BLOCK	0x1
156#define	L2_TABLE	L1_TABLE
157
158/* Level 3 table, 4KiB/16KiB per entry */
159#define	L3_SIZE 	(1 << L3_SHIFT)
160#define	L3_OFFSET 	(L3_SIZE - 1)
161#define	L3_INVAL	0x0
162	/* 0x1 is reserved */
163	/* 0x2 also marks an invalid address */
164#define	L3_PAGE		0x3
165
166/*
167 * A substantial portion of this is to make sure that we can cope with 4K
168 * framebuffers in early boot, assuming a common 4K resolution @ 32-bit depth.
169 */
170#define	PMAP_MAPDEV_EARLY_SIZE	(L2_SIZE * 20)
171
172#if PAGE_SIZE == PAGE_SIZE_4K
173#define	L0_ENTRIES_SHIFT 9
174#define	Ln_ENTRIES_SHIFT 9
175#elif PAGE_SIZE == PAGE_SIZE_16K
176#define	L0_ENTRIES_SHIFT 1
177#define	Ln_ENTRIES_SHIFT 11
178#else
179#error Unsupported page size
180#endif
181
182#define	L0_ENTRIES	(1 << L0_ENTRIES_SHIFT)
183#define	L0_ADDR_MASK	(L0_ENTRIES - 1)
184
185#define	Ln_ENTRIES	(1 << Ln_ENTRIES_SHIFT)
186#define	Ln_ADDR_MASK	(Ln_ENTRIES - 1)
187#define	Ln_TABLE_MASK	((1 << 12) - 1)
188
189#define	pmap_l0_index(va)	(((va) >> L0_SHIFT) & L0_ADDR_MASK)
190#define	pmap_l1_index(va)	(((va) >> L1_SHIFT) & Ln_ADDR_MASK)
191#define	pmap_l2_index(va)	(((va) >> L2_SHIFT) & Ln_ADDR_MASK)
192#define	pmap_l3_index(va)	(((va) >> L3_SHIFT) & Ln_ADDR_MASK)
193
194#endif /* !_MACHINE_PTE_H_ */
195
196/* End of pte.h */
197
198#endif /* !__arm__ */