master
1/*-
2 * Copyright (c) 2013, 2014 Andrew Turner
3 * Copyright (c) 2021 The FreeBSD Foundation
4 *
5 * Portions of this software were developed by Andrew Turner
6 * under sponsorship from the FreeBSD Foundation.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30#ifndef _MACHINE_HYPERVISOR_H_
31#define _MACHINE_HYPERVISOR_H_
32
33/*
34 * These registers are only useful when in hypervisor context,
35 * e.g. specific to EL2, or controlling the hypervisor.
36 */
37
38/* CNTHCTL_EL2 - Counter-timer Hypervisor Control register */
39#define CNTHCTL_EVNTI_MASK (0xf << 4) /* Bit to trigger event stream */
40/* Valid if HCR_EL2.E2H == 0 */
41#define CNTHCTL_EL1PCTEN (1 << 0) /* Allow physical counter access */
42#define CNTHCTL_EL1PCEN (1 << 1) /* Allow physical timer access */
43/* Valid if HCR_EL2.E2H == 1 */
44#define CNTHCTL_E2H_EL1PCTEN (1 << 10) /* Allow physical counter access */
45#define CNTHCTL_E2H_EL1PTEN (1 << 11) /* Allow physical timer access */
46/* Unconditionally valid */
47#define CNTHCTL_EVNTDIR (1 << 3) /* Control transition trigger bit */
48#define CNTHCTL_EVNTEN (1 << 2) /* Enable event stream */
49
50/* CPTR_EL2 - Architecture feature trap register */
51/* Valid if HCR_EL2.E2H == 0 */
52#define CPTR_RES0 0x7fefc800
53#define CPTR_RES1 0x000032ff
54#define CPTR_TFP 0x00000400
55/* Valid if HCR_EL2.E2H == 1 */
56#define CPTR_FPEN 0x00300000
57/* Unconditionally valid */
58#define CPTR_TTA 0x00100000
59#define CPTR_TCPAC 0x80000000
60
61/* HCR_EL2 - Hypervisor Config Register */
62#define HCR_VM (UL(0x1) << 0)
63#define HCR_SWIO (UL(0x1) << 1)
64#define HCR_PTW (UL(0x1) << 2)
65#define HCR_FMO (UL(0x1) << 3)
66#define HCR_IMO (UL(0x1) << 4)
67#define HCR_AMO (UL(0x1) << 5)
68#define HCR_VF (UL(0x1) << 6)
69#define HCR_VI (UL(0x1) << 7)
70#define HCR_VSE (UL(0x1) << 8)
71#define HCR_FB (UL(0x1) << 9)
72#define HCR_BSU_MASK (UL(0x3) << 10)
73#define HCR_BSU_IS (UL(0x1) << 10)
74#define HCR_BSU_OS (UL(0x2) << 10)
75#define HCR_BSU_FS (UL(0x3) << 10)
76#define HCR_DC (UL(0x1) << 12)
77#define HCR_TWI (UL(0x1) << 13)
78#define HCR_TWE (UL(0x1) << 14)
79#define HCR_TID0 (UL(0x1) << 15)
80#define HCR_TID1 (UL(0x1) << 16)
81#define HCR_TID2 (UL(0x1) << 17)
82#define HCR_TID3 (UL(0x1) << 18)
83#define HCR_TSC (UL(0x1) << 19)
84#define HCR_TIDCP (UL(0x1) << 20)
85#define HCR_TACR (UL(0x1) << 21)
86#define HCR_TSW (UL(0x1) << 22)
87#define HCR_TPCP (UL(0x1) << 23)
88#define HCR_TPU (UL(0x1) << 24)
89#define HCR_TTLB (UL(0x1) << 25)
90#define HCR_TVM (UL(0x1) << 26)
91#define HCR_TGE (UL(0x1) << 27)
92#define HCR_TDZ (UL(0x1) << 28)
93#define HCR_HCD (UL(0x1) << 29)
94#define HCR_TRVM (UL(0x1) << 30)
95#define HCR_RW (UL(0x1) << 31)
96#define HCR_CD (UL(0x1) << 32)
97#define HCR_ID (UL(0x1) << 33)
98#define HCR_E2H (UL(0x1) << 34)
99#define HCR_TLOR (UL(0x1) << 35)
100#define HCR_TERR (UL(0x1) << 36)
101#define HCR_TEA (UL(0x1) << 37)
102#define HCR_MIOCNCE (UL(0x1) << 38)
103/* Bit 39 is reserved */
104#define HCR_APK (UL(0x1) << 40)
105#define HCR_API (UL(0x1) << 41)
106#define HCR_NV (UL(0x1) << 42)
107#define HCR_NV1 (UL(0x1) << 43)
108#define HCR_AT (UL(0x1) << 44)
109#define HCR_NV2 (UL(0x1) << 45)
110#define HCR_FWB (UL(0x1) << 46)
111#define HCR_FIEN (UL(0x1) << 47)
112/* Bit 48 is reserved */
113#define HCR_TID4 (UL(0x1) << 49)
114#define HCR_TICAB (UL(0x1) << 50)
115#define HCR_AMVOFFEN (UL(0x1) << 51)
116#define HCR_TOCU (UL(0x1) << 52)
117#define HCR_EnSCXT (UL(0x1) << 53)
118#define HCR_TTLBIS (UL(0x1) << 54)
119#define HCR_TTLBOS (UL(0x1) << 55)
120#define HCR_ATA (UL(0x1) << 56)
121#define HCR_DCT (UL(0x1) << 57)
122#define HCR_TID5 (UL(0x1) << 58)
123#define HCR_TWEDEn (UL(0x1) << 59)
124#define HCR_TWEDEL_MASK (UL(0xf) << 60)
125
126/* HPFAR_EL2 - Hypervisor IPA Fault Address Register */
127#define HPFAR_EL2_FIPA_SHIFT 4
128#define HPFAR_EL2_FIPA_MASK 0xfffffffff0
129#define HPFAR_EL2_FIPA_GET(x) \
130 (((x) & HPFAR_EL2_FIPA_MASK) >> HPFAR_EL2_FIPA_SHIFT)
131/* HPFAR_EL2_FIPA holds the 4k page address */
132#define HPFAR_EL2_FIPA_ADDR(x) \
133 (HPFAR_EL2_FIPA_GET(x) << 12)
134/* The bits from FAR_EL2 we need to add to HPFAR_EL2_FIPA_ADDR */
135#define FAR_EL2_HPFAR_PAGE_MASK (0xffful)
136
137/* ICC_SRE_EL2 */
138#define ICC_SRE_EL2_SRE (1UL << 0)
139#define ICC_SRE_EL2_EN (1UL << 3)
140
141/* SCTLR_EL2 - System Control Register */
142#define SCTLR_EL2_RES1 0x30c50830
143#define SCTLR_EL2_M_SHIFT 0
144#define SCTLR_EL2_M (0x1UL << SCTLR_EL2_M_SHIFT)
145#define SCTLR_EL2_A_SHIFT 1
146#define SCTLR_EL2_A (0x1UL << SCTLR_EL2_A_SHIFT)
147#define SCTLR_EL2_C_SHIFT 2
148#define SCTLR_EL2_C (0x1UL << SCTLR_EL2_C_SHIFT)
149#define SCTLR_EL2_SA_SHIFT 3
150#define SCTLR_EL2_SA (0x1UL << SCTLR_EL2_SA_SHIFT)
151#define SCTLR_EL2_EOS_SHIFT 11
152#define SCTLR_EL2_EOS (0x1UL << SCTLR_EL2_EOS_SHIFT)
153#define SCTLR_EL2_I_SHIFT 12
154#define SCTLR_EL2_I (0x1UL << SCTLR_EL2_I_SHIFT)
155#define SCTLR_EL2_WXN_SHIFT 19
156#define SCTLR_EL2_WXN (0x1UL << SCTLR_EL2_WXN_SHIFT)
157#define SCTLR_EL2_EIS_SHIFT 22
158#define SCTLR_EL2_EIS (0x1UL << SCTLR_EL2_EIS_SHIFT)
159#define SCTLR_EL2_EE_SHIFT 25
160#define SCTLR_EL2_EE (0x1UL << SCTLR_EL2_EE_SHIFT)
161
162/* TCR_EL2 - Translation Control Register */
163#define TCR_EL2_RES1 ((0x1UL << 31) | (0x1UL << 23))
164#define TCR_EL2_T0SZ_SHIFT 0
165#define TCR_EL2_T0SZ_MASK (0x3fUL << TCR_EL2_T0SZ_SHIFT)
166#define TCR_EL2_T0SZ(x) ((x) << TCR_EL2_T0SZ_SHIFT)
167/* Bits 7:6 are reserved */
168#define TCR_EL2_IRGN0_SHIFT 8
169#define TCR_EL2_IRGN0_MASK (0x3UL << TCR_EL2_IRGN0_SHIFT)
170#define TCR_EL2_IRGN0_WBWA (1UL << TCR_EL2_IRGN0_SHIFT)
171#define TCR_EL2_ORGN0_SHIFT 10
172#define TCR_EL2_ORGN0_MASK (0x3UL << TCR_EL2_ORGN0_SHIFT)
173#define TCR_EL2_ORGN0_WBWA (1UL << TCR_EL2_ORGN0_SHIFT)
174#define TCR_EL2_SH0_SHIFT 12
175#define TCR_EL2_SH0_MASK (0x3UL << TCR_EL2_SH0_SHIFT)
176#define TCR_EL2_SH0_IS (3UL << TCR_EL2_SH0_SHIFT)
177#define TCR_EL2_TG0_SHIFT 14
178#define TCR_EL2_TG0_MASK (0x3UL << TCR_EL2_TG0_SHIFT)
179#define TCR_EL2_TG0_4K (0x0UL << TCR_EL2_TG0_SHIFT)
180#define TCR_EL2_TG0_64K (0x1UL << TCR_EL2_TG0_SHIFT)
181#define TCR_EL2_TG0_16K (0x2UL << TCR_EL2_TG0_SHIFT)
182#define TCR_EL2_PS_SHIFT 16
183#define TCR_EL2_PS_MASK (0xfUL << TCR_EL2_PS_SHIFT)
184#define TCR_EL2_PS_32BITS (0UL << TCR_EL2_PS_SHIFT)
185#define TCR_EL2_PS_36BITS (1UL << TCR_EL2_PS_SHIFT)
186#define TCR_EL2_PS_40BITS (2UL << TCR_EL2_PS_SHIFT)
187#define TCR_EL2_PS_42BITS (3UL << TCR_EL2_PS_SHIFT)
188#define TCR_EL2_PS_44BITS (4UL << TCR_EL2_PS_SHIFT)
189#define TCR_EL2_PS_48BITS (5UL << TCR_EL2_PS_SHIFT)
190#define TCR_EL2_PS_52BITS (6UL << TCR_EL2_PS_SHIFT)
191#define TCR_EL2_HPD_SHIFT 24
192#define TCR_EL2_HPD (1UL << TCR_EL2_HPD_SHIFT)
193#define TCR_EL2_HWU59_SHIFT 25
194#define TCR_EL2_HWU59 (1UL << TCR_EL2_HWU59_SHIFT)
195#define TCR_EL2_HWU60_SHIFT 26
196#define TCR_EL2_HWU60 (1UL << TCR_EL2_HWU60_SHIFT)
197#define TCR_EL2_HWU61_SHIFT 27
198#define TCR_EL2_HWU61 (1UL << TCR_EL2_HWU61_SHIFT)
199#define TCR_EL2_HWU62_SHIFT 28
200#define TCR_EL2_HWU62 (1UL << TCR_EL2_HWU62_SHIFT)
201#define TCR_EL2_HWU \
202 (TCR_EL2_HWU59 | TCR_EL2_HWU60 | TCR_EL2_HWU61 | TCR_EL2_HWU62)
203
204/* VMPDIR_EL2 - Virtualization Multiprocessor ID Register */
205#define VMPIDR_EL2_U 0x0000000040000000
206#define VMPIDR_EL2_MT 0x0000000001000000
207#define VMPIDR_EL2_RES1 0x0000000080000000
208
209/* VTCR_EL2 - Virtualization Translation Control Register */
210#define VTCR_EL2_RES1 (0x1UL << 31)
211#define VTCR_EL2_T0SZ_SHIFT 0
212#define VTCR_EL2_T0SZ_MASK (0x3fUL << VTCR_EL2_T0SZ_SHIFT)
213#define VTCR_EL2_T0SZ(x) ((x) << VTCR_EL2_T0SZ_SHIFT)
214#define VTCR_EL2_SL0_SHIFT 6
215#define VTCR_EL2_SL0_4K_LVL2 (0x0UL << VTCR_EL2_SL0_SHIFT)
216#define VTCR_EL2_SL0_4K_LVL1 (0x1UL << VTCR_EL2_SL0_SHIFT)
217#define VTCR_EL2_SL0_4K_LVL0 (0x2UL << VTCR_EL2_SL0_SHIFT)
218#define VTCR_EL2_SL0_16K_LVL2 (0x1UL << VTCR_EL2_SL0_SHIFT)
219#define VTCR_EL2_SL0_16K_LVL1 (0x2UL << VTCR_EL2_SL0_SHIFT)
220#define VTCR_EL2_SL0_16K_LVL0 (0x3UL << VTCR_EL2_SL0_SHIFT)
221#define VTCR_EL2_IRGN0_SHIFT 8
222#define VTCR_EL2_IRGN0_WBWA (0x1UL << VTCR_EL2_IRGN0_SHIFT)
223#define VTCR_EL2_ORGN0_SHIFT 10
224#define VTCR_EL2_ORGN0_WBWA (0x1UL << VTCR_EL2_ORGN0_SHIFT)
225#define VTCR_EL2_SH0_SHIFT 12
226#define VTCR_EL2_SH0_NS (0x0UL << VTCR_EL2_SH0_SHIFT)
227#define VTCR_EL2_SH0_OS (0x2UL << VTCR_EL2_SH0_SHIFT)
228#define VTCR_EL2_SH0_IS (0x3UL << VTCR_EL2_SH0_SHIFT)
229#define VTCR_EL2_TG0_SHIFT 14
230#define VTCR_EL2_TG0_4K (0x0UL << VTCR_EL2_TG0_SHIFT)
231#define VTCR_EL2_TG0_64K (0x1UL << VTCR_EL2_TG0_SHIFT)
232#define VTCR_EL2_TG0_16K (0x2UL << VTCR_EL2_TG0_SHIFT)
233#define VTCR_EL2_PS_SHIFT 16
234#define VTCR_EL2_PS_32BIT (0x0UL << VTCR_EL2_PS_SHIFT)
235#define VTCR_EL2_PS_36BIT (0x1UL << VTCR_EL2_PS_SHIFT)
236#define VTCR_EL2_PS_40BIT (0x2UL << VTCR_EL2_PS_SHIFT)
237#define VTCR_EL2_PS_42BIT (0x3UL << VTCR_EL2_PS_SHIFT)
238#define VTCR_EL2_PS_44BIT (0x4UL << VTCR_EL2_PS_SHIFT)
239#define VTCR_EL2_PS_48BIT (0x5UL << VTCR_EL2_PS_SHIFT)
240
241/* VTTBR_EL2 - Virtualization Translation Table Base Register */
242#define VTTBR_VMID_MASK 0xffff000000000000
243#define VTTBR_VMID_SHIFT 48
244/* Assumed to be 0 by locore.S */
245#define VTTBR_HOST 0x0000000000000000
246
247/* MDCR_EL2 - Hyp Debug Control Register */
248#define MDCR_EL2_HPMN_MASK 0x1f
249#define MDCR_EL2_HPMN_SHIFT 0
250#define MDCR_EL2_TPMCR_SHIFT 5
251#define MDCR_EL2_TPMCR (0x1UL << MDCR_EL2_TPMCR_SHIFT)
252#define MDCR_EL2_TPM_SHIFT 6
253#define MDCR_EL2_TPM (0x1UL << MDCR_EL2_TPM_SHIFT)
254#define MDCR_EL2_HPME_SHIFT 7
255#define MDCR_EL2_HPME (0x1UL << MDCR_EL2_HPME_SHIFT)
256#define MDCR_EL2_TDE_SHIFT 8
257#define MDCR_EL2_TDE (0x1UL << MDCR_EL2_TDE_SHIFT)
258#define MDCR_EL2_TDA_SHIFT 9
259#define MDCR_EL2_TDA (0x1UL << MDCR_EL2_TDA_SHIFT)
260#define MDCR_EL2_TDOSA_SHIFT 10
261#define MDCR_EL2_TDOSA (0x1UL << MDCR_EL2_TDOSA_SHIFT)
262#define MDCR_EL2_TDRA_SHIFT 11
263#define MDCR_EL2_TDRA (0x1UL << MDCR_EL2_TDRA_SHIFT)
264#define MDCR_E2PB_SHIFT 12
265#define MDCR_E2PB_MASK (0x3UL << MDCR_E2PB_SHIFT)
266#define MDCR_TPMS_SHIFT 14
267#define MDCR_TPMS (0x1UL << MDCR_TPMS_SHIFT)
268#define MDCR_EnSPM_SHIFT 15
269#define MDCR_EnSPM (0x1UL << MDCR_EnSPM_SHIFT)
270#define MDCR_HPMD_SHIFT 17
271#define MDCR_HPMD (0x1UL << MDCR_HPMD_SHIFT)
272#define MDCR_TTRF_SHIFT 19
273#define MDCR_TTRF (0x1UL << MDCR_TTRF_SHIFT)
274#define MDCR_HCCD_SHIFT 23
275#define MDCR_HCCD (0x1UL << MDCR_HCCD_SHIFT)
276#define MDCR_E2TB_SHIFT 24
277#define MDCR_E2TB_MASK (0x3UL << MDCR_E2TB_SHIFT)
278#define MDCR_HLP_SHIFT 26
279#define MDCR_HLP (0x1UL << MDCR_HLP_SHIFT)
280#define MDCR_TDCC_SHIFT 27
281#define MDCR_TDCC (0x1UL << MDCR_TDCC_SHIFT)
282#define MDCR_MTPME_SHIFT 28
283#define MDCR_MTPME (0x1UL << MDCR_MTPME_SHIFT)
284#define MDCR_HPMFZO_SHIFT 29
285#define MDCR_HPMFZO (0x1UL << MDCR_HPMFZO_SHIFT)
286#define MDCR_PMSSE_SHIFT 30
287#define MDCR_PMSSE_MASK (0x3UL << MDCR_PMSSE_SHIFT)
288#define MDCR_HPMFZS_SHIFT 36
289#define MDCR_HPMFZS (0x1UL << MDCR_HPMFZS_SHIFT)
290#define MDCR_PMEE_SHIFT 40
291#define MDCR_PMEE_MASK (0x3UL << MDCR_PMEE_SHIFT)
292#define MDCR_EBWE_SHIFT 43
293#define MDCR_EBWE (0x1UL << MDCR_EBWE_SHIFT)
294
295#endif /* !_MACHINE_HYPERVISOR_H_ */