master
1/*-
2 * Copyright (c) 2014 Andrew Turner
3 * Copyright (c) 2014-2015 The FreeBSD Foundation
4 * All rights reserved.
5 *
6 * This software was developed by Semihalf under
7 * sponsorship from the FreeBSD Foundation.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31#ifndef _MACHINE_DB_MACHDEP_H_
32#define _MACHINE_DB_MACHDEP_H_
33
34#include <machine/armreg.h>
35#include <machine/frame.h>
36#include <machine/trap.h>
37
38#define T_BREAKPOINT (EXCP_BRK)
39#define T_HW_BREAKPOINT (EXCP_BRKPT_EL1)
40#define T_SINGLESTEP (EXCP_SOFTSTP_EL1)
41#define T_WATCHPOINT (EXCP_WATCHPT_EL1)
42
43typedef vm_offset_t db_addr_t;
44typedef long db_expr_t;
45
46#define PC_REGS() ((db_addr_t)kdb_thrctx->pcb_x[PCB_LR])
47
48#define BKPT_INST (0xd4200000)
49#define BKPT_SIZE (4)
50#define BKPT_SET(inst) (BKPT_INST)
51
52#define BKPT_SKIP do { \
53 kdb_frame->tf_elr += BKPT_SIZE; \
54 kdb_thrctx->pcb_x[PCB_LR] += BKPT_SIZE; \
55} while (0)
56
57#define db_clear_single_step kdb_cpu_clear_singlestep
58#define db_set_single_step kdb_cpu_set_singlestep
59
60#define IS_BREAKPOINT_TRAP(type, code) \
61 (type == T_BREAKPOINT || type == T_HW_BREAKPOINT)
62#define IS_SSTEP_TRAP(type, code) (type == T_SINGLESTEP)
63#define IS_WATCHPOINT_TRAP(type, code) (type == T_WATCHPOINT)
64
65#define inst_trap_return(ins) (0)
66/* ret */
67#define inst_return(ins) (((ins) & 0xfffffc1fu) == 0xd65f0000)
68#define inst_call(ins) (((ins) & 0xfc000000u) == 0x94000000u || /* BL */ \
69 ((ins) & 0xfffffc1fu) == 0xd63f0000u) /* BLR */
70
71#define inst_load(ins) ({ \
72 uint32_t tmp_instr = db_get_value(PC_REGS(), sizeof(uint32_t), FALSE); \
73 is_load_instr(tmp_instr); \
74})
75
76#define inst_store(ins) ({ \
77 uint32_t tmp_instr = db_get_value(PC_REGS(), sizeof(uint32_t), FALSE); \
78 is_store_instr(tmp_instr); \
79})
80
81#define is_load_instr(ins) ((((ins) & 0x3b000000u) == 0x18000000u) || /* literal */ \
82 (((ins) & 0x3f400000u) == 0x08400000u) || /* exclusive */ \
83 (((ins) & 0x3bc00000u) == 0x28400000u) || /* no-allocate pair */ \
84 ((((ins) & 0x3b200c00u) == 0x38000400u) && \
85 (((ins) & 0x3be00c00u) != 0x38000400u) && \
86 (((ins) & 0xffe00c00u) != 0x3c800400u)) || /* immediate post-indexed */ \
87 ((((ins) & 0x3b200c00u) == 0x38000c00u) && \
88 (((ins) & 0x3be00c00u) != 0x38000c00u) && \
89 (((ins) & 0xffe00c00u) != 0x3c800c00u)) || /* immediate pre-indexed */ \
90 ((((ins) & 0x3b200c00u) == 0x38200800u) && \
91 (((ins) & 0x3be00c00u) != 0x38200800u) && \
92 (((ins) & 0xffe00c00u) != 0x3ca00c80u)) || /* register offset */ \
93 ((((ins) & 0x3b200c00u) == 0x38000800u) && \
94 (((ins) & 0x3be00c00u) != 0x38000800u)) || /* unprivileged */ \
95 ((((ins) & 0x3b200c00u) == 0x38000000u) && \
96 (((ins) & 0x3be00c00u) != 0x38000000u) && \
97 (((ins) & 0xffe00c00u) != 0x3c800000u)) || /* unscaled immediate */ \
98 ((((ins) & 0x3b000000u) == 0x39000000u) && \
99 (((ins) & 0x3bc00000u) != 0x39000000u) && \
100 (((ins) & 0xffc00000u) != 0x3d800000u)) || /* unsigned immediate */ \
101 (((ins) & 0x3bc00000u) == 0x28400000u) || /* pair (offset) */ \
102 (((ins) & 0x3bc00000u) == 0x28c00000u) || /* pair (post-indexed) */ \
103 (((ins) & 0x3bc00000u) == 0x29800000u)) /* pair (pre-indexed) */
104
105#define is_store_instr(ins) ((((ins) & 0x3f400000u) == 0x08000000u) || /* exclusive */ \
106 (((ins) & 0x3bc00000u) == 0x28000000u) || /* no-allocate pair */ \
107 ((((ins) & 0x3be00c00u) == 0x38000400u) || \
108 (((ins) & 0xffe00c00u) == 0x3c800400u)) || /* immediate post-indexed */ \
109 ((((ins) & 0x3be00c00u) == 0x38000c00u) || \
110 (((ins) & 0xffe00c00u) == 0x3c800c00u)) || /* immediate pre-indexed */ \
111 ((((ins) & 0x3be00c00u) == 0x38200800u) || \
112 (((ins) & 0xffe00c00u) == 0x3ca00800u)) || /* register offset */ \
113 (((ins) & 0x3be00c00u) == 0x38000800u) || /* unprivileged */ \
114 ((((ins) & 0x3be00c00u) == 0x38000000u) || \
115 (((ins) & 0xffe00c00u) == 0x3c800000u)) || /* unscaled immediate */ \
116 ((((ins) & 0x3bc00000u) == 0x39000000u) || \
117 (((ins) & 0xffc00000u) == 0x3d800000u)) || /* unsigned immediate */ \
118 (((ins) & 0x3bc00000u) == 0x28000000u) || /* pair (offset) */ \
119 (((ins) & 0x3bc00000u) == 0x28800000u) || /* pair (post-indexed) */ \
120 (((ins) & 0x3bc00000u) == 0x29800000u)) /* pair (pre-indexed) */
121
122#define next_instr_address(pc, bd) ((bd) ? (pc) : ((pc) + 4))
123
124#define DB_ELFSIZE 64
125
126#endif /* !_MACHINE_DB_MACHDEP_H_ */