1/*-
   2 * Copyright (c) 2013, 2014 Andrew Turner
   3 * Copyright (c) 2015,2021 The FreeBSD Foundation
   4 *
   5 * Portions of this software were developed by Andrew Turner
   6 * under sponsorship from the FreeBSD Foundation.
   7 *
   8 * Redistribution and use in source and binary forms, with or without
   9 * modification, are permitted provided that the following conditions
  10 * are met:
  11 * 1. Redistributions of source code must retain the above copyright
  12 *    notice, this list of conditions and the following disclaimer.
  13 * 2. Redistributions in binary form must reproduce the above copyright
  14 *    notice, this list of conditions and the following disclaimer in the
  15 *    documentation and/or other materials provided with the distribution.
  16 *
  17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  20 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  27 * SUCH DAMAGE.
  28 */
  29
  30#ifdef __arm__
  31#include <arm/armreg.h>
  32#else /* !__arm__ */
  33
  34#ifndef _MACHINE_ARMREG_H_
  35#define	_MACHINE_ARMREG_H_
  36
  37#define	INSN_SIZE		4
  38
  39#define	MRS_MASK			0xfff00000
  40#define	MRS_VALUE			0xd5300000
  41#define	MRS_SPECIAL(insn)		((insn) & 0x000fffe0)
  42#define	MRS_REGISTER(insn)		((insn) & 0x0000001f)
  43#define	 MRS_Op0_SHIFT			19
  44#define	 MRS_Op0_MASK			0x00080000
  45#define	 MRS_Op1_SHIFT			16
  46#define	 MRS_Op1_MASK			0x00070000
  47#define	 MRS_CRn_SHIFT			12
  48#define	 MRS_CRn_MASK			0x0000f000
  49#define	 MRS_CRm_SHIFT			8
  50#define	 MRS_CRm_MASK			0x00000f00
  51#define	 MRS_Op2_SHIFT			5
  52#define	 MRS_Op2_MASK			0x000000e0
  53#define	 MRS_Rt_SHIFT			0
  54#define	 MRS_Rt_MASK			0x0000001f
  55#define	__MRS_REG(op0, op1, crn, crm, op2)				\
  56    (((op0) << MRS_Op0_SHIFT) | ((op1) << MRS_Op1_SHIFT) |		\
  57     ((crn) << MRS_CRn_SHIFT) | ((crm) << MRS_CRm_SHIFT) |		\
  58     ((op2) << MRS_Op2_SHIFT))
  59#define	MRS_REG(reg)							\
  60    __MRS_REG(reg##_op0, reg##_op1, reg##_CRn, reg##_CRm, reg##_op2)
  61
  62#define	__MRS_REG_ALT_NAME(op0, op1, crn, crm, op2)			\
  63    S##op0##_##op1##_C##crn##_C##crm##_##op2
  64#define	_MRS_REG_ALT_NAME(op0, op1, crn, crm, op2)			\
  65    __MRS_REG_ALT_NAME(op0, op1, crn, crm, op2)
  66#define	MRS_REG_ALT_NAME(reg)						\
  67    _MRS_REG_ALT_NAME(reg##_op0, reg##_op1, reg##_CRn, reg##_CRm, reg##_op2)
  68
  69
  70#define	READ_SPECIALREG(reg)						\
  71({	uint64_t _val;							\
  72	__asm __volatile("mrs	%0, " __STRING(reg) : "=&r" (_val));	\
  73	_val;								\
  74})
  75#define	WRITE_SPECIALREG(reg, _val)					\
  76	__asm __volatile("msr	" __STRING(reg) ", %0" : : "r"((uint64_t)_val))
  77
  78#define	UL(x)	UINT64_C(x)
  79
  80/* AFSR0_EL1 - Auxiliary Fault Status Register 0 */
  81#define	AFSR0_EL1_REG			MRS_REG_ALT_NAME(AFSR0_EL1)
  82#define	AFSR0_EL1_op0			3
  83#define	AFSR0_EL1_op1			0
  84#define	AFSR0_EL1_CRn			5
  85#define	AFSR0_EL1_CRm			1
  86#define	AFSR0_EL1_op2			0
  87
  88/* AFSR0_EL12 */
  89#define	AFSR0_EL12_REG			MRS_REG_ALT_NAME(AFSR0_EL12)
  90#define	AFSR0_EL12_op0			3
  91#define	AFSR0_EL12_op1			5
  92#define	AFSR0_EL12_CRn			5
  93#define	AFSR0_EL12_CRm			1
  94#define	AFSR0_EL12_op2			0
  95
  96/* AFSR1_EL1 - Auxiliary Fault Status Register 1 */
  97#define	AFSR1_EL1_REG			MRS_REG_ALT_NAME(AFSR1_EL1)
  98#define	AFSR1_EL1_op0			3
  99#define	AFSR1_EL1_op1			0
 100#define	AFSR1_EL1_CRn			5
 101#define	AFSR1_EL1_CRm			1
 102#define	AFSR1_EL1_op2			1
 103
 104/* AFSR1_EL12 */
 105#define	AFSR1_EL12_REG			MRS_REG_ALT_NAME(AFSR1_EL12)
 106#define	AFSR1_EL12_op0			3
 107#define	AFSR1_EL12_op1			5
 108#define	AFSR1_EL12_CRn			5
 109#define	AFSR1_EL12_CRm			1
 110#define	AFSR1_EL12_op2			1
 111
 112/* AMAIR_EL1 - Auxiliary Memory Attribute Indirection Register */
 113#define	AMAIR_EL1_REG			MRS_REG_ALT_NAME(AMAIR_EL1)
 114#define	AMAIR_EL1_op0			3
 115#define	AMAIR_EL1_op1			0
 116#define	AMAIR_EL1_CRn			10
 117#define	AMAIR_EL1_CRm			3
 118#define	AMAIR_EL1_op2			0
 119
 120/* AMAIR_EL12 */
 121#define	AMAIR_EL12_REG			MRS_REG_ALT_NAME(AMAIR_EL12)
 122#define	AMAIR_EL12_op0			3
 123#define	AMAIR_EL12_op1			5
 124#define	AMAIR_EL12_CRn			10
 125#define	AMAIR_EL12_CRm			3
 126#define	AMAIR_EL12_op2			0
 127
 128/* APDAKeyHi_EL1 */
 129#define	APDAKeyHi_EL1_REG	MRS_REG_ALT_NAME(APDAKeyHi_EL1)
 130#define	APDAKeyHi_EL1_op0	3
 131#define	APDAKeyHi_EL1_op1	0
 132#define	APDAKeyHi_EL1_CRn	2
 133#define	APDAKeyHi_EL1_CRm	2
 134#define	APDAKeyHi_EL1_op2	1
 135
 136/* APDAKeyLo_EL1 */
 137#define	APDAKeyLo_EL1_REG	MRS_REG_ALT_NAME(APDAKeyLo_EL1)
 138#define	APDAKeyLo_EL1_op0	3
 139#define	APDAKeyLo_EL1_op1	0
 140#define	APDAKeyLo_EL1_CRn	2
 141#define	APDAKeyLo_EL1_CRm	2
 142#define	APDAKeyLo_EL1_op2	0
 143
 144/* APDBKeyHi_EL1 */
 145#define	APDBKeyHi_EL1_REG	MRS_REG_ALT_NAME(APDBKeyHi_EL1)
 146#define	APDBKeyHi_EL1_op0	3
 147#define	APDBKeyHi_EL1_op1	0
 148#define	APDBKeyHi_EL1_CRn	2
 149#define	APDBKeyHi_EL1_CRm	2
 150#define	APDBKeyHi_EL1_op2	3
 151
 152/* APDBKeyLo_EL1 */
 153#define	APDBKeyLo_EL1_REG	MRS_REG_ALT_NAME(APDBKeyLo_EL1)
 154#define	APDBKeyLo_EL1_op0	3
 155#define	APDBKeyLo_EL1_op1	0
 156#define	APDBKeyLo_EL1_CRn	2
 157#define	APDBKeyLo_EL1_CRm	2
 158#define	APDBKeyLo_EL1_op2	2
 159
 160/* APGAKeyHi_EL1 */
 161#define	APGAKeyHi_EL1_REG	MRS_REG_ALT_NAME(APGAKeyHi_EL1)
 162#define	APGAKeyHi_EL1_op0	3
 163#define	APGAKeyHi_EL1_op1	0
 164#define	APGAKeyHi_EL1_CRn	2
 165#define	APGAKeyHi_EL1_CRm	3
 166#define	APGAKeyHi_EL1_op2	1
 167
 168/* APGAKeyLo_EL1 */
 169#define	APGAKeyLo_EL1_REG	MRS_REG_ALT_NAME(APGAKeyLo_EL1)
 170#define	APGAKeyLo_EL1_op0	3
 171#define	APGAKeyLo_EL1_op1	0
 172#define	APGAKeyLo_EL1_CRn	2
 173#define	APGAKeyLo_EL1_CRm	3
 174#define	APGAKeyLo_EL1_op2	0
 175
 176/* APIAKeyHi_EL1 */
 177#define	APIAKeyHi_EL1_REG	MRS_REG_ALT_NAME(APIAKeyHi_EL1)
 178#define	APIAKeyHi_EL1_op0	3
 179#define	APIAKeyHi_EL1_op1	0
 180#define	APIAKeyHi_EL1_CRn	2
 181#define	APIAKeyHi_EL1_CRm	1
 182#define	APIAKeyHi_EL1_op2	1
 183
 184/* APIAKeyLo_EL1 */
 185#define	APIAKeyLo_EL1_REG	MRS_REG_ALT_NAME(APIAKeyLo_EL1)
 186#define	APIAKeyLo_EL1_op0	3
 187#define	APIAKeyLo_EL1_op1	0
 188#define	APIAKeyLo_EL1_CRn	2
 189#define	APIAKeyLo_EL1_CRm	1
 190#define	APIAKeyLo_EL1_op2	0
 191
 192/* APIBKeyHi_EL1 */
 193#define	APIBKeyHi_EL1_REG	MRS_REG_ALT_NAME(APIBKeyHi_EL1)
 194#define	APIBKeyHi_EL1_op0	3
 195#define	APIBKeyHi_EL1_op1	0
 196#define	APIBKeyHi_EL1_CRn	2
 197#define	APIBKeyHi_EL1_CRm	1
 198#define	APIBKeyHi_EL1_op2	3
 199
 200/* APIBKeyLo_EL1 */
 201#define	APIBKeyLo_EL1_REG	MRS_REG_ALT_NAME(APIBKeyLo_EL1)
 202#define	APIBKeyLo_EL1_op0	3
 203#define	APIBKeyLo_EL1_op1	0
 204#define	APIBKeyLo_EL1_CRn	2
 205#define	APIBKeyLo_EL1_CRm	1
 206#define	APIBKeyLo_EL1_op2	2
 207
 208/* CCSIDR_EL1 - Cache Size ID Register */
 209#define	CCSIDR_NumSets_MASK	0x0FFFE000
 210#define	CCSIDR_NumSets64_MASK	0x00FFFFFF00000000
 211#define	CCSIDR_NumSets_SHIFT	13
 212#define	CCSIDR_NumSets64_SHIFT	32
 213#define	CCSIDR_Assoc_MASK	0x00001FF8
 214#define	CCSIDR_Assoc64_MASK	0x0000000000FFFFF8
 215#define	CCSIDR_Assoc_SHIFT	3
 216#define	CCSIDR_Assoc64_SHIFT	3
 217#define	CCSIDR_LineSize_MASK	0x7
 218#define	CCSIDR_NSETS(idr)						\
 219	(((idr) & CCSIDR_NumSets_MASK) >> CCSIDR_NumSets_SHIFT)
 220#define	CCSIDR_ASSOC(idr)						\
 221	(((idr) & CCSIDR_Assoc_MASK) >> CCSIDR_Assoc_SHIFT)
 222#define	CCSIDR_NSETS_64(idr)						\
 223	(((idr) & CCSIDR_NumSets64_MASK) >> CCSIDR_NumSets64_SHIFT)
 224#define	CCSIDR_ASSOC_64(idr)						\
 225	(((idr) & CCSIDR_Assoc64_MASK) >> CCSIDR_Assoc64_SHIFT)
 226
 227/* CLIDR_EL1 - Cache level ID register */
 228#define	CLIDR_CTYPE_MASK	0x7	/* Cache type mask bits */
 229#define	CLIDR_CTYPE_IO		0x1	/* Instruction only */
 230#define	CLIDR_CTYPE_DO		0x2	/* Data only */
 231#define	CLIDR_CTYPE_ID		0x3	/* Split instruction and data */
 232#define	CLIDR_CTYPE_UNIFIED	0x4	/* Unified */
 233
 234/* CNTP_CTL_EL0 - Counter-timer Physical Timer Control register */
 235#define	CNTP_CTL_EL0		MRS_REG(CNTP_CTL_EL0)
 236#define	CNTP_CTL_EL0_op0	3
 237#define	CNTP_CTL_EL0_op1	3
 238#define	CNTP_CTL_EL0_CRn	14
 239#define	CNTP_CTL_EL0_CRm	2
 240#define	CNTP_CTL_EL0_op2	1
 241#define	CNTP_CTL_ENABLE		(1 << 0)
 242#define	CNTP_CTL_IMASK		(1 << 1)
 243#define	CNTP_CTL_ISTATUS	(1 << 2)
 244
 245/* CNTP_CVAL_EL0 - Counter-timer Physical Timer CompareValue register */
 246#define	CNTP_CVAL_EL0		MRS_REG(CNTP_CVAL_EL0)
 247#define	CNTP_CVAL_EL0_op0	3
 248#define	CNTP_CVAL_EL0_op1	3
 249#define	CNTP_CVAL_EL0_CRn	14
 250#define	CNTP_CVAL_EL0_CRm	2
 251#define	CNTP_CVAL_EL0_op2	2
 252
 253/* CNTP_TVAL_EL0 - Counter-timer Physical Timer TimerValue register */
 254#define	CNTP_TVAL_EL0		MRS_REG(CNTP_TVAL_EL0)
 255#define	CNTP_TVAL_EL0_op0	3
 256#define	CNTP_TVAL_EL0_op1	3
 257#define	CNTP_TVAL_EL0_CRn	14
 258#define	CNTP_TVAL_EL0_CRm	2
 259#define	CNTP_TVAL_EL0_op2	0
 260
 261/* CNTPCT_EL0 - Counter-timer Physical Count register */
 262#define	CNTPCT_EL0		MRS_REG(CNTPCT_EL0)
 263#define	CNTPCT_EL0_op0		3
 264#define	CNTPCT_EL0_op1		3
 265#define	CNTPCT_EL0_CRn		14
 266#define	CNTPCT_EL0_CRm		0
 267#define	CNTPCT_EL0_op2		1
 268
 269/* CONTEXTIDR_EL1 - Context ID register */
 270#define	CONTEXTIDR_EL1		MRS_REG(CONTEXTIDR_EL1)
 271#define	CONTEXTIDR_EL1_REG	MRS_REG_ALT_NAME(CONTEXTIDR_EL1)
 272#define	CONTEXTIDR_EL1_op0	3
 273#define	CONTEXTIDR_EL1_op1	0
 274#define	CONTEXTIDR_EL1_CRn	13
 275#define	CONTEXTIDR_EL1_CRm	0
 276#define	CONTEXTIDR_EL1_op2	1
 277
 278/* CONTEXTIDR_EL12 */
 279#define	CONTEXTIDR_EL12_REG	MRS_REG_ALT_NAME(CONTEXTIDR_EL12)
 280#define	CONTEXTIDR_EL12_op0	3
 281#define	CONTEXTIDR_EL12_op1	5
 282#define	CONTEXTIDR_EL12_CRn	13
 283#define	CONTEXTIDR_EL12_CRm	0
 284#define	CONTEXTIDR_EL12_op2	1
 285
 286/* CPACR_EL1 */
 287#define	CPACR_EL1_REG		MRS_REG_ALT_NAME(CPACR_EL1)
 288#define	CPACR_EL1_op0		3
 289#define	CPACR_EL1_op1		0
 290#define	CPACR_EL1_CRn		1
 291#define	CPACR_EL1_CRm		0
 292#define	CPACR_EL1_op2		2
 293#define	CPACR_ZEN_MASK		(0x3 << 16)
 294#define	 CPACR_ZEN_TRAP_ALL1	(0x0 << 16) /* Traps from EL0 and EL1 */
 295#define	 CPACR_ZEN_TRAP_EL0	(0x1 << 16) /* Traps from EL0 */
 296#define	 CPACR_ZEN_TRAP_ALL2	(0x2 << 16) /* Traps from EL0 and EL1 */
 297#define	 CPACR_ZEN_TRAP_NONE	(0x3 << 16) /* No traps */
 298#define	CPACR_FPEN_MASK		(0x3 << 20)
 299#define	 CPACR_FPEN_TRAP_ALL1	(0x0 << 20) /* Traps from EL0 and EL1 */
 300#define	 CPACR_FPEN_TRAP_EL0	(0x1 << 20) /* Traps from EL0 */
 301#define	 CPACR_FPEN_TRAP_ALL2	(0x2 << 20) /* Traps from EL0 and EL1 */
 302#define	 CPACR_FPEN_TRAP_NONE	(0x3 << 20) /* No traps */
 303#define	CPACR_TTA		(0x1 << 28)
 304
 305/* CPACR_EL12 */
 306#define	CPACR_EL12_REG		MRS_REG_ALT_NAME(CPACR_EL12)
 307#define	CPACR_EL12_op0		3
 308#define	CPACR_EL12_op1		5
 309#define	CPACR_EL12_CRn		1
 310#define	CPACR_EL12_CRm		0
 311#define	CPACR_EL12_op2		2
 312
 313/* CSSELR_EL1 - Cache size selection register */
 314#define	CSSELR_Level(i)		(i << 1)
 315#define	CSSELR_InD		0x00000001
 316
 317/* CTR_EL0 - Cache Type Register */
 318#define	CTR_RES1		(1 << 31)
 319#define	CTR_TminLine_SHIFT	32
 320#define	CTR_TminLine_MASK	(UL(0x3f) << CTR_TminLine_SHIFT)
 321#define	CTR_TminLine_VAL(reg)	((reg) & CTR_TminLine_MASK)
 322#define	CTR_DIC_SHIFT		29
 323#define	CTR_DIC_MASK		(0x1 << CTR_DIC_SHIFT)
 324#define	CTR_DIC_VAL(reg)	((reg) & CTR_DIC_MASK)
 325#define	CTR_IDC_SHIFT		28
 326#define	CTR_IDC_MASK		(0x1 << CTR_IDC_SHIFT)
 327#define	CTR_IDC_VAL(reg)	((reg) & CTR_IDC_MASK)
 328#define	CTR_CWG_SHIFT		24
 329#define	CTR_CWG_MASK		(0xf << CTR_CWG_SHIFT)
 330#define	CTR_CWG_VAL(reg)	((reg) & CTR_CWG_MASK)
 331#define	CTR_CWG_SIZE(reg)	(4 << (CTR_CWG_VAL(reg) >> CTR_CWG_SHIFT))
 332#define	CTR_ERG_SHIFT		20
 333#define	CTR_ERG_MASK		(0xf << CTR_ERG_SHIFT)
 334#define	CTR_ERG_VAL(reg)	((reg) & CTR_ERG_MASK)
 335#define	CTR_ERG_SIZE(reg)	(4 << (CTR_ERG_VAL(reg) >> CTR_ERG_SHIFT))
 336#define	CTR_DLINE_SHIFT		16
 337#define	CTR_DLINE_MASK		(0xf << CTR_DLINE_SHIFT)
 338#define	CTR_DLINE_VAL(reg)	((reg) & CTR_DLINE_MASK)
 339#define	CTR_DLINE_SIZE(reg)	(4 << (CTR_DLINE_VAL(reg) >> CTR_DLINE_SHIFT))
 340#define	CTR_L1IP_SHIFT		14
 341#define	CTR_L1IP_MASK		(0x3 << CTR_L1IP_SHIFT)
 342#define	CTR_L1IP_VAL(reg)	((reg) & CTR_L1IP_MASK)
 343#define	 CTR_L1IP_VPIPT		(0 << CTR_L1IP_SHIFT)
 344#define	 CTR_L1IP_AIVIVT	(1 << CTR_L1IP_SHIFT)
 345#define	 CTR_L1IP_VIPT		(2 << CTR_L1IP_SHIFT)
 346#define	 CTR_L1IP_PIPT		(3 << CTR_L1IP_SHIFT)
 347#define	CTR_ILINE_SHIFT		0
 348#define	CTR_ILINE_MASK		(0xf << CTR_ILINE_SHIFT)
 349#define	CTR_ILINE_VAL(reg)	((reg) & CTR_ILINE_MASK)
 350#define	CTR_ILINE_SIZE(reg)	(4 << (CTR_ILINE_VAL(reg) >> CTR_ILINE_SHIFT))
 351
 352/* CurrentEL - Current Exception Level */
 353#define	CURRENTEL_EL_SHIFT	2
 354#define	CURRENTEL_EL_MASK	(0x3 << CURRENTEL_EL_SHIFT)
 355#define	 CURRENTEL_EL_EL0	(0x0 << CURRENTEL_EL_SHIFT)
 356#define	 CURRENTEL_EL_EL1	(0x1 << CURRENTEL_EL_SHIFT)
 357#define	 CURRENTEL_EL_EL2	(0x2 << CURRENTEL_EL_SHIFT)
 358#define	 CURRENTEL_EL_EL3	(0x3 << CURRENTEL_EL_SHIFT)
 359
 360/* DAIFSet/DAIFClear */
 361#define	DAIF_D			(1 << 3)
 362#define	DAIF_A			(1 << 2)
 363#define	DAIF_I			(1 << 1)
 364#define	DAIF_F			(1 << 0)
 365#define	DAIF_ALL		(DAIF_D | DAIF_A | DAIF_I | DAIF_F)
 366#define	DAIF_INTR		(DAIF_I)	/* All exceptions that pass */
 367						/* through the intr framework */
 368
 369/* DBGBCR<n>_EL1 - Debug Breakpoint Control Registers */
 370#define	DBGBCR_EL1_op0		2
 371#define	DBGBCR_EL1_op1		0
 372#define	DBGBCR_EL1_CRn		0
 373/* DBGBCR_EL1_CRm indicates which watchpoint this register is for */
 374#define	DBGBCR_EL1_op2		5
 375#define	DBGBCR_EN		0x1
 376#define	DBGBCR_PMC_SHIFT	1
 377#define	DBGBCR_PMC		(0x3 << DBGBCR_PMC_SHIFT)
 378#define	 DBGBCR_PMC_EL1		(0x1 << DBGBCR_PMC_SHIFT)
 379#define	 DBGBCR_PMC_EL0		(0x2 << DBGBCR_PMC_SHIFT)
 380#define	DBGBCR_BAS_SHIFT	5
 381#define	DBGBCR_BAS		(0xf << DBGBCR_BAS_SHIFT)
 382#define	DBGBCR_HMC_SHIFT	13
 383#define	DBGBCR_HMC		(0x1 << DBGBCR_HMC_SHIFT)
 384#define	DBGBCR_SSC_SHIFT	14
 385#define	DBGBCR_SSC		(0x3 << DBGBCR_SSC_SHIFT)
 386#define	DBGBCR_LBN_SHIFT	16
 387#define	DBGBCR_LBN		(0xf << DBGBCR_LBN_SHIFT)
 388#define	DBGBCR_BT_SHIFT		20
 389#define	DBGBCR_BT		(0xf << DBGBCR_BT_SHIFT)
 390
 391/* DBGBVR<n>_EL1 - Debug Breakpoint Value Registers */
 392#define	DBGBVR_EL1_op0		2
 393#define	DBGBVR_EL1_op1		0
 394#define	DBGBVR_EL1_CRn		0
 395/* DBGBVR_EL1_CRm indicates which watchpoint this register is for */
 396#define	DBGBVR_EL1_op2		4
 397
 398/* DBGWCR<n>_EL1 - Debug Watchpoint Control Registers */
 399#define	DBGWCR_EL1_op0		2
 400#define	DBGWCR_EL1_op1		0
 401#define	DBGWCR_EL1_CRn		0
 402/* DBGWCR_EL1_CRm indicates which watchpoint this register is for */
 403#define	DBGWCR_EL1_op2		7
 404#define	DBGWCR_EN		0x1
 405#define	DBGWCR_PAC_SHIFT	1
 406#define	DBGWCR_PAC		(0x3 << DBGWCR_PAC_SHIFT)
 407#define	 DBGWCR_PAC_EL1		(0x1 << DBGWCR_PAC_SHIFT)
 408#define	 DBGWCR_PAC_EL0		(0x2 << DBGWCR_PAC_SHIFT)
 409#define	DBGWCR_LSC_SHIFT	3
 410#define	DBGWCR_LSC		(0x3 << DBGWCR_LSC_SHIFT)
 411#define	DBGWCR_BAS_SHIFT	5
 412#define	DBGWCR_BAS		(0xff << DBGWCR_BAS_SHIFT)
 413#define	DBGWCR_HMC_SHIFT	13
 414#define	DBGWCR_HMC		(0x1 << DBGWCR_HMC_SHIFT)
 415#define	DBGWCR_SSC_SHIFT	14
 416#define	DBGWCR_SSC		(0x3 << DBGWCR_SSC_SHIFT)
 417#define	DBGWCR_LBN_SHIFT	16
 418#define	DBGWCR_LBN		(0xf << DBGWCR_LBN_SHIFT)
 419#define	DBGWCR_WT_SHIFT		20
 420#define	DBGWCR_WT		(0x1 << DBGWCR_WT_SHIFT)
 421#define	DBGWCR_MASK_SHIFT	24
 422#define	DBGWCR_MASK		(0x1f << DBGWCR_MASK_SHIFT)
 423
 424/* DBGWVR<n>_EL1 - Debug Watchpoint Value Registers */
 425#define	DBGWVR_EL1_op0		2
 426#define	DBGWVR_EL1_op1		0
 427#define	DBGWVR_EL1_CRn		0
 428/* DBGWVR_EL1_CRm indicates which watchpoint this register is for */
 429#define	DBGWVR_EL1_op2		6
 430
 431/* DCZID_EL0 - Data Cache Zero ID register */
 432#define DCZID_DZP		(1 << 4) /* DC ZVA prohibited if non-0 */
 433#define DCZID_BS_SHIFT		0
 434#define DCZID_BS_MASK		(0xf << DCZID_BS_SHIFT)
 435#define	DCZID_BS_SIZE(reg)	(((reg) & DCZID_BS_MASK) >> DCZID_BS_SHIFT)
 436
 437/* DBGAUTHSTATUS_EL1 */
 438#define	DBGAUTHSTATUS_EL1		MRS_REG(DBGAUTHSTATUS_EL1)
 439#define	DBGAUTHSTATUS_EL1_op0		2
 440#define	DBGAUTHSTATUS_EL1_op1		0
 441#define	DBGAUTHSTATUS_EL1_CRn		7
 442#define	DBGAUTHSTATUS_EL1_CRm		14
 443#define	DBGAUTHSTATUS_EL1_op2		6
 444
 445/* DBGCLAIMCLR_EL1 */
 446#define	DBGCLAIMCLR_EL1			MRS_REG(DBGCLAIMCLR_EL1)
 447#define	DBGCLAIMCLR_EL1_op0		2
 448#define	DBGCLAIMCLR_EL1_op1		0
 449#define	DBGCLAIMCLR_EL1_CRn		7
 450#define	DBGCLAIMCLR_EL1_CRm		9
 451#define	DBGCLAIMCLR_EL1_op2		6
 452
 453/* DBGCLAIMSET_EL1 */
 454#define	DBGCLAIMSET_EL1			MRS_REG(DBGCLAIMSET_EL1)
 455#define	DBGCLAIMSET_EL1_op0		2
 456#define	DBGCLAIMSET_EL1_op1		0
 457#define	DBGCLAIMSET_EL1_CRn		7
 458#define	DBGCLAIMSET_EL1_CRm		8
 459#define	DBGCLAIMSET_EL1_op2		6
 460
 461/* DBGPRCR_EL1 */
 462#define	DBGPRCR_EL1			MRS_REG(DBGPRCR_EL1)
 463#define	DBGPRCR_EL1_op0			2
 464#define	DBGPRCR_EL1_op1			0
 465#define	DBGPRCR_EL1_CRn			1
 466#define	DBGPRCR_EL1_CRm			4
 467#define	DBGPRCR_EL1_op2			4
 468
 469/* ELR_EL1 */
 470#define	ELR_EL1_REG			MRS_REG_ALT_NAME(ELR_EL1)
 471#define	ELR_EL1_op0			3
 472#define	ELR_EL1_op1			0
 473#define	ELR_EL1_CRn			4
 474#define	ELR_EL1_CRm			0
 475#define	ELR_EL1_op2			1
 476
 477/* ELR_EL12 */
 478#define	ELR_EL12_REG			MRS_REG_ALT_NAME(ELR_EL12)
 479#define	ELR_EL12_op0			3
 480#define	ELR_EL12_op1			5
 481#define	ELR_EL12_CRn			4
 482#define	ELR_EL12_CRm			0
 483#define	ELR_EL12_op2			1
 484
 485/* ESR_ELx */
 486#define	ESR_ELx_ISS_MASK	0x01ffffff
 487#define	 ISS_FP_TFV_SHIFT	23
 488#define	 ISS_FP_TFV		(0x01 << ISS_FP_TFV_SHIFT)
 489#define	 ISS_FP_IOF		0x01
 490#define	 ISS_FP_DZF		0x02
 491#define	 ISS_FP_OFF		0x04
 492#define	 ISS_FP_UFF		0x08
 493#define	 ISS_FP_IXF		0x10
 494#define	 ISS_FP_IDF		0x80
 495#define	 ISS_INSN_FnV		(0x01 << 10)
 496#define	 ISS_INSN_EA		(0x01 << 9)
 497#define	 ISS_INSN_S1PTW		(0x01 << 7)
 498#define	 ISS_INSN_IFSC_MASK	(0x1f << 0)
 499
 500#define	 ISS_WFx_TI_SHIFT	0
 501#define	 ISS_WFx_TI_MASK	(0x03 << ISS_WFx_TI_SHIFT)
 502#define	 ISS_WFx_TI_WFI		(0x00 << ISS_WFx_TI_SHIFT)
 503#define	 ISS_WFx_TI_WFE		(0x01 << ISS_WFx_TI_SHIFT)
 504#define	 ISS_WFx_TI_WFIT	(0x02 << ISS_WFx_TI_SHIFT)
 505#define	 ISS_WFx_TI_WFET	(0x03 << ISS_WFx_TI_SHIFT)
 506#define	 ISS_WFx_RV_SHIFT	2
 507#define	 ISS_WFx_RV_MASK	(0x01 << ISS_WFx_RV_SHIFT)
 508#define	 ISS_WFx_RV_INVALID	(0x00 << ISS_WFx_RV_SHIFT)
 509#define	 ISS_WFx_RV_VALID	(0x01 << ISS_WFx_RV_SHIFT)
 510#define	 ISS_WFx_RN_SHIFT	5
 511#define	 ISS_WFx_RN_MASK	(0x1f << ISS_WFx_RN_SHIFT)
 512#define	 ISS_WFx_RN(x)		(((x) & ISS_WFx_RN_MASK) >> ISS_WFx_RN_SHIFT)
 513#define	 ISS_WFx_COND_SHIFT	20
 514#define	 ISS_WFx_COND_MASK	(0x0f << ISS_WFx_COND_SHIFT)
 515#define	 ISS_WFx_CV_SHIFT	24
 516#define	 ISS_WFx_CV_MASK	(0x01 << ISS_WFx_CV_SHIFT)
 517#define	 ISS_WFx_CV_INVALID	(0x00 << ISS_WFx_CV_SHIFT)
 518#define	 ISS_WFx_CV_VALID	(0x01 << ISS_WFx_CV_SHIFT)
 519
 520#define	 ISS_MSR_DIR_SHIFT	0
 521#define	 ISS_MSR_DIR		(0x01 << ISS_MSR_DIR_SHIFT)
 522#define	 ISS_MSR_Rt_SHIFT	5
 523#define	 ISS_MSR_Rt_MASK	(0x1f << ISS_MSR_Rt_SHIFT)
 524#define	 ISS_MSR_Rt(x)		(((x) & ISS_MSR_Rt_MASK) >> ISS_MSR_Rt_SHIFT)
 525#define	 ISS_MSR_CRm_SHIFT	1
 526#define	 ISS_MSR_CRm_MASK	(0xf << ISS_MSR_CRm_SHIFT)
 527#define	 ISS_MSR_CRm(x)		(((x) & ISS_MSR_CRm_MASK) >> ISS_MSR_CRm_SHIFT)
 528#define	 ISS_MSR_CRn_SHIFT	10
 529#define	 ISS_MSR_CRn_MASK	(0xf << ISS_MSR_CRn_SHIFT)
 530#define	 ISS_MSR_CRn(x)		(((x) & ISS_MSR_CRn_MASK) >> ISS_MSR_CRn_SHIFT)
 531#define	 ISS_MSR_OP1_SHIFT	14
 532#define	 ISS_MSR_OP1_MASK	(0x7 << ISS_MSR_OP1_SHIFT)
 533#define	 ISS_MSR_OP1(x)		(((x) & ISS_MSR_OP1_MASK) >> ISS_MSR_OP1_SHIFT)
 534#define	 ISS_MSR_OP2_SHIFT	17
 535#define	 ISS_MSR_OP2_MASK	(0x7 << ISS_MSR_OP2_SHIFT)
 536#define	 ISS_MSR_OP2(x)		(((x) & ISS_MSR_OP2_MASK) >> ISS_MSR_OP2_SHIFT)
 537#define	 ISS_MSR_OP0_SHIFT	20
 538#define	 ISS_MSR_OP0_MASK	(0x3 << ISS_MSR_OP0_SHIFT)
 539#define	 ISS_MSR_OP0(x)		(((x) & ISS_MSR_OP0_MASK) >> ISS_MSR_OP0_SHIFT)
 540#define	 ISS_MSR_REG_MASK	\
 541    (ISS_MSR_OP0_MASK | ISS_MSR_OP2_MASK | ISS_MSR_OP1_MASK | 	\
 542     ISS_MSR_CRn_MASK | ISS_MSR_CRm_MASK)
 543#define	 ISS_MSR_REG(reg)				\
 544    (((reg ## _op0) << ISS_MSR_OP0_SHIFT) |		\
 545     ((reg ## _op1) << ISS_MSR_OP1_SHIFT) |		\
 546     ((reg ## _CRn) << ISS_MSR_CRn_SHIFT) |		\
 547     ((reg ## _CRm) << ISS_MSR_CRm_SHIFT) |		\
 548     ((reg ## _op2) << ISS_MSR_OP2_SHIFT))
 549
 550#define	 ISS_DATA_ISV_SHIFT	24
 551#define	 ISS_DATA_ISV		(0x01 << ISS_DATA_ISV_SHIFT)
 552#define	 ISS_DATA_SAS_SHIFT	22
 553#define	 ISS_DATA_SAS_MASK	(0x03 << ISS_DATA_SAS_SHIFT)
 554#define	 ISS_DATA_SSE_SHIFT	21
 555#define	 ISS_DATA_SSE		(0x01 << ISS_DATA_SSE_SHIFT)
 556#define	 ISS_DATA_SRT_SHIFT	16
 557#define	 ISS_DATA_SRT_MASK	(0x1f << ISS_DATA_SRT_SHIFT)
 558#define	 ISS_DATA_SF		(0x01 << 15)
 559#define	 ISS_DATA_AR		(0x01 << 14)
 560#define	 ISS_DATA_FnV		(0x01 << 10)
 561#define	 ISS_DATA_EA		(0x01 << 9)
 562#define	 ISS_DATA_CM		(0x01 << 8)
 563#define	 ISS_DATA_S1PTW		(0x01 << 7)
 564#define	 ISS_DATA_WnR_SHIFT	6
 565#define	 ISS_DATA_WnR		(0x01 << ISS_DATA_WnR_SHIFT)
 566#define	 ISS_DATA_DFSC_MASK	(0x3f << 0)
 567#define	 ISS_DATA_DFSC_ASF_L0	(0x00 << 0)
 568#define	 ISS_DATA_DFSC_ASF_L1	(0x01 << 0)
 569#define	 ISS_DATA_DFSC_ASF_L2	(0x02 << 0)
 570#define	 ISS_DATA_DFSC_ASF_L3	(0x03 << 0)
 571#define	 ISS_DATA_DFSC_TF_L0	(0x04 << 0)
 572#define	 ISS_DATA_DFSC_TF_L1	(0x05 << 0)
 573#define	 ISS_DATA_DFSC_TF_L2	(0x06 << 0)
 574#define	 ISS_DATA_DFSC_TF_L3	(0x07 << 0)
 575#define	 ISS_DATA_DFSC_AFF_L1	(0x09 << 0)
 576#define	 ISS_DATA_DFSC_AFF_L2	(0x0a << 0)
 577#define	 ISS_DATA_DFSC_AFF_L3	(0x0b << 0)
 578#define	 ISS_DATA_DFSC_PF_L1	(0x0d << 0)
 579#define	 ISS_DATA_DFSC_PF_L2	(0x0e << 0)
 580#define	 ISS_DATA_DFSC_PF_L3	(0x0f << 0)
 581#define	 ISS_DATA_DFSC_EXT	(0x10 << 0)
 582#define	 ISS_DATA_DFSC_EXT_L0	(0x14 << 0)
 583#define	 ISS_DATA_DFSC_EXT_L1	(0x15 << 0)
 584#define	 ISS_DATA_DFSC_EXT_L2	(0x16 << 0)
 585#define	 ISS_DATA_DFSC_EXT_L3	(0x17 << 0)
 586#define	 ISS_DATA_DFSC_ECC	(0x18 << 0)
 587#define	 ISS_DATA_DFSC_ECC_L0	(0x1c << 0)
 588#define	 ISS_DATA_DFSC_ECC_L1	(0x1d << 0)
 589#define	 ISS_DATA_DFSC_ECC_L2	(0x1e << 0)
 590#define	 ISS_DATA_DFSC_ECC_L3	(0x1f << 0)
 591#define	 ISS_DATA_DFSC_ALIGN	(0x21 << 0)
 592#define	 ISS_DATA_DFSC_TLB_CONFLICT (0x30 << 0)
 593#define	ESR_ELx_IL		(0x01 << 25)
 594#define	ESR_ELx_EC_SHIFT	26
 595#define	ESR_ELx_EC_MASK		(0x3f << 26)
 596#define	ESR_ELx_EXCEPTION(esr)	(((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT)
 597#define	 EXCP_UNKNOWN		0x00	/* Unkwn exception */
 598#define	 EXCP_TRAP_WFI_WFE	0x01	/* Trapped WFI or WFE */
 599#define	 EXCP_FP_SIMD		0x07	/* VFP/SIMD trap */
 600#define	 EXCP_BTI		0x0d	/* Branch Target Exception */
 601#define	 EXCP_ILL_STATE		0x0e	/* Illegal execution state */
 602#define	 EXCP_SVC32		0x11	/* SVC trap for AArch32 */
 603#define	 EXCP_SVC64		0x15	/* SVC trap for AArch64 */
 604#define	 EXCP_HVC		0x16	/* HVC trap */
 605#define	 EXCP_MSR		0x18	/* MSR/MRS trap */
 606#define	 EXCP_SVE		0x19	/* SVE trap */
 607#define	 EXCP_FPAC		0x1c	/* Faulting PAC trap */
 608#define	 EXCP_INSN_ABORT_L	0x20	/* Instruction abort, from lower EL */
 609#define	 EXCP_INSN_ABORT	0x21	/* Instruction abort, from same EL */ 
 610#define	 EXCP_PC_ALIGN		0x22	/* PC alignment fault */
 611#define	 EXCP_DATA_ABORT_L	0x24	/* Data abort, from lower EL */
 612#define	 EXCP_DATA_ABORT	0x25	/* Data abort, from same EL */ 
 613#define	 EXCP_SP_ALIGN		0x26	/* SP slignment fault */
 614#define	 EXCP_TRAP_FP		0x2c	/* Trapped FP exception */
 615#define	 EXCP_SERROR		0x2f	/* SError interrupt */
 616#define	 EXCP_BRKPT_EL0		0x30	/* Hardware breakpoint, from same EL */
 617#define	 EXCP_BRKPT_EL1		0x31	/* Hardware breakpoint, from same EL */
 618#define	 EXCP_SOFTSTP_EL0	0x32	/* Software Step, from lower EL */
 619#define	 EXCP_SOFTSTP_EL1	0x33	/* Software Step, from same EL */
 620#define	 EXCP_WATCHPT_EL0	0x34	/* Watchpoint, from lower EL */
 621#define	 EXCP_WATCHPT_EL1	0x35	/* Watchpoint, from same EL */
 622#define	 EXCP_BRKPT_32		0x38    /* 32bits breakpoint */
 623#define	 EXCP_BRK		0x3c	/* Breakpoint */
 624
 625/* ESR_EL1 */
 626#define	ESR_EL1_REG			MRS_REG_ALT_NAME(ESR_EL1)
 627#define	ESR_EL1_op0			3
 628#define	ESR_EL1_op1			0
 629#define	ESR_EL1_CRn			5
 630#define	ESR_EL1_CRm			2
 631#define	ESR_EL1_op2			0
 632
 633/* ESR_EL12 */
 634#define	ESR_EL12_REG			MRS_REG_ALT_NAME(ESR_EL12)
 635#define	ESR_EL12_op0			3
 636#define	ESR_EL12_op1			5
 637#define	ESR_EL12_CRn			5
 638#define	ESR_EL12_CRm			2
 639#define	ESR_EL12_op2			0
 640
 641/* FAR_EL1 */
 642#define	FAR_EL1_REG			MRS_REG_ALT_NAME(FAR_EL1)
 643#define	FAR_EL1_op0			3
 644#define	FAR_EL1_op1			0
 645#define	FAR_EL1_CRn			6
 646#define	FAR_EL1_CRm			0
 647#define	FAR_EL1_op2			0
 648
 649/* FAR_EL12 */
 650#define	FAR_EL12_REG			MRS_REG_ALT_NAME(FAR_EL12)
 651#define	FAR_EL12_op0			3
 652#define	FAR_EL12_op1			5
 653#define	FAR_EL12_CRn			6
 654#define	FAR_EL12_CRm			0
 655#define	FAR_EL12_op2			0
 656
 657/* ICC_CTLR_EL1 */
 658#define	ICC_CTLR_EL1_EOIMODE	(1U << 1)
 659
 660/* ICC_IAR1_EL1 */
 661#define	ICC_IAR1_EL1_SPUR	(0x03ff)
 662
 663/* ICC_IGRPEN0_EL1 */
 664#define	ICC_IGRPEN0_EL1_EN	(1U << 0)
 665
 666/* ICC_PMR_EL1 */
 667#define	ICC_PMR_EL1_PRIO_MASK	(0xFFUL)
 668
 669/* ICC_SGI1R_EL1 */
 670#define	ICC_SGI1R_EL1			MRS_REG(ICC_SGI1R_EL1)
 671#define	ICC_SGI1R_EL1_op0		3
 672#define	ICC_SGI1R_EL1_op1		0
 673#define	ICC_SGI1R_EL1_CRn		12
 674#define	ICC_SGI1R_EL1_CRm		11
 675#define	ICC_SGI1R_EL1_op2		5
 676#define	ICC_SGI1R_EL1_TL_SHIFT		0
 677#define	ICC_SGI1R_EL1_TL_MASK		(0xffffUL << ICC_SGI1R_EL1_TL_SHIFT)
 678#define	ICC_SGI1R_EL1_TL_VAL(x)		((x) & ICC_SGI1R_EL1_TL_MASK)
 679#define	ICC_SGI1R_EL1_AFF1_SHIFT	16
 680#define	ICC_SGI1R_EL1_AFF1_MASK		(0xfful << ICC_SGI1R_EL1_AFF1_SHIFT)
 681#define	ICC_SGI1R_EL1_AFF1_VAL(x)	((x) & ICC_SGI1R_EL1_AFF1_MASK)
 682#define	ICC_SGI1R_EL1_SGIID_SHIFT	24
 683#define	ICC_SGI1R_EL1_SGIID_MASK	(0xfUL << ICC_SGI1R_EL1_SGIID_SHIFT)
 684#define	ICC_SGI1R_EL1_SGIID_VAL(x)	((x) & ICC_SGI1R_EL1_SGIID_MASK)
 685#define	ICC_SGI1R_EL1_AFF2_SHIFT	32
 686#define	ICC_SGI1R_EL1_AFF2_MASK		(0xfful << ICC_SGI1R_EL1_AFF2_SHIFT)
 687#define	ICC_SGI1R_EL1_AFF2_VAL(x)	((x) & ICC_SGI1R_EL1_AFF2_MASK)
 688#define	ICC_SGI1R_EL1_RS_SHIFT		44
 689#define	ICC_SGI1R_EL1_RS_MASK		(0xful << ICC_SGI1R_EL1_RS_SHIFT)
 690#define	ICC_SGI1R_EL1_RS_VAL(x)		((x) & ICC_SGI1R_EL1_RS_MASK)
 691#define	ICC_SGI1R_EL1_AFF3_SHIFT	48
 692#define	ICC_SGI1R_EL1_AFF3_MASK		(0xfful << ICC_SGI1R_EL1_AFF3_SHIFT)
 693#define	ICC_SGI1R_EL1_AFF3_VAL(x)	((x) & ICC_SGI1R_EL1_AFF3_MASK)
 694#define	ICC_SGI1R_EL1_IRM		(0x1UL << 40)
 695
 696/* ICC_SRE_EL1 */
 697#define	ICC_SRE_EL1_SRE		(1U << 0)
 698
 699/* ID_AA64AFR0_EL1 */
 700#define	ID_AA64AFR0_EL1			MRS_REG(ID_AA64AFR0_EL1)
 701#define	ID_AA64AFR0_EL1_REG		MRS_REG_ALT_NAME(ID_AA64AFR0_EL1)
 702#define	ID_AA64AFR0_EL1_op0		3
 703#define	ID_AA64AFR0_EL1_op1		0
 704#define	ID_AA64AFR0_EL1_CRn		0
 705#define	ID_AA64AFR0_EL1_CRm		5
 706#define	ID_AA64AFR0_EL1_op2		4
 707
 708/* ID_AA64AFR1_EL1 */
 709#define	ID_AA64AFR1_EL1			MRS_REG(ID_AA64AFR1_EL1)
 710#define	ID_AA64AFR1_EL1_REG		MRS_REG_ALT_NAME(ID_AA64AFR1_EL1)
 711#define	ID_AA64AFR1_EL1_op0		3
 712#define	ID_AA64AFR1_EL1_op1		0
 713#define	ID_AA64AFR1_EL1_CRn		0
 714#define	ID_AA64AFR1_EL1_CRm		5
 715#define	ID_AA64AFR1_EL1_op2		5
 716
 717/* ID_AA64DFR0_EL1 */
 718#define	ID_AA64DFR0_EL1			MRS_REG(ID_AA64DFR0_EL1)
 719#define	ID_AA64DFR0_EL1_REG		MRS_REG_ALT_NAME(ID_AA64DFR0_EL1)
 720#define	ID_AA64DFR0_EL1_op0		3
 721#define	ID_AA64DFR0_EL1_op1		0
 722#define	ID_AA64DFR0_EL1_CRn		0
 723#define	ID_AA64DFR0_EL1_CRm		5
 724#define	ID_AA64DFR0_EL1_op2		0
 725#define	ID_AA64DFR0_DebugVer_SHIFT	0
 726#define	ID_AA64DFR0_DebugVer_MASK	(UL(0xf) << ID_AA64DFR0_DebugVer_SHIFT)
 727#define	ID_AA64DFR0_DebugVer_VAL(x)	((x) & ID_AA64DFR0_DebugVer_MASK)
 728#define	 ID_AA64DFR0_DebugVer_8		(UL(0x6) << ID_AA64DFR0_DebugVer_SHIFT)
 729#define	 ID_AA64DFR0_DebugVer_8_VHE	(UL(0x7) << ID_AA64DFR0_DebugVer_SHIFT)
 730#define	 ID_AA64DFR0_DebugVer_8_2	(UL(0x8) << ID_AA64DFR0_DebugVer_SHIFT)
 731#define	 ID_AA64DFR0_DebugVer_8_4	(UL(0x9) << ID_AA64DFR0_DebugVer_SHIFT)
 732#define	 ID_AA64DFR0_DebugVer_8_8	(UL(0xa) << ID_AA64DFR0_DebugVer_SHIFT)
 733#define	ID_AA64DFR0_TraceVer_SHIFT	4
 734#define	ID_AA64DFR0_TraceVer_MASK	(UL(0xf) << ID_AA64DFR0_TraceVer_SHIFT)
 735#define	ID_AA64DFR0_TraceVer_VAL(x)	((x) & ID_AA64DFR0_TraceVer_MASK)
 736#define	 ID_AA64DFR0_TraceVer_NONE	(UL(0x0) << ID_AA64DFR0_TraceVer_SHIFT)
 737#define	 ID_AA64DFR0_TraceVer_IMPL	(UL(0x1) << ID_AA64DFR0_TraceVer_SHIFT)
 738#define	ID_AA64DFR0_PMUVer_SHIFT	8
 739#define	ID_AA64DFR0_PMUVer_MASK		(UL(0xf) << ID_AA64DFR0_PMUVer_SHIFT)
 740#define	ID_AA64DFR0_PMUVer_VAL(x)	((x) & ID_AA64DFR0_PMUVer_MASK)
 741#define	 ID_AA64DFR0_PMUVer_NONE	(UL(0x0) << ID_AA64DFR0_PMUVer_SHIFT)
 742#define	 ID_AA64DFR0_PMUVer_3		(UL(0x1) << ID_AA64DFR0_PMUVer_SHIFT)
 743#define	 ID_AA64DFR0_PMUVer_3_1		(UL(0x4) << ID_AA64DFR0_PMUVer_SHIFT)
 744#define	 ID_AA64DFR0_PMUVer_3_4		(UL(0x5) << ID_AA64DFR0_PMUVer_SHIFT)
 745#define	 ID_AA64DFR0_PMUVer_3_5		(UL(0x6) << ID_AA64DFR0_PMUVer_SHIFT)
 746#define	 ID_AA64DFR0_PMUVer_3_7		(UL(0x7) << ID_AA64DFR0_PMUVer_SHIFT)
 747#define	 ID_AA64DFR0_PMUVer_3_8		(UL(0x8) << ID_AA64DFR0_PMUVer_SHIFT)
 748#define	 ID_AA64DFR0_PMUVer_IMPL	(UL(0xf) << ID_AA64DFR0_PMUVer_SHIFT)
 749#define	ID_AA64DFR0_BRPs_SHIFT		12
 750#define	ID_AA64DFR0_BRPs_MASK		(UL(0xf) << ID_AA64DFR0_BRPs_SHIFT)
 751#define	ID_AA64DFR0_BRPs_VAL(x)	\
 752    ((((x) >> ID_AA64DFR0_BRPs_SHIFT) & 0xf) + 1)
 753#define	ID_AA64DFR0_PMSS_SHIFT		16
 754#define	ID_AA64DFR0_PMSS_MASK		(UL(0xf) << ID_AA64DFR0_PMSS_SHIFT)
 755#define	ID_AA64DFR0_PMSS_VAL(x)		((x) & ID_AA64DFR0_PMSS_MASK)
 756#define	 ID_AA64DFR0_PMSS_NONE		(UL(0x0) << ID_AA64DFR0_PMSS_SHIFT)
 757#define	 ID_AA64DFR0_PMSS_IMPL		(UL(0x1) << ID_AA64DFR0_PMSS_SHIFT)
 758#define	ID_AA64DFR0_WRPs_SHIFT		20
 759#define	ID_AA64DFR0_WRPs_MASK		(UL(0xf) << ID_AA64DFR0_WRPs_SHIFT)
 760#define	ID_AA64DFR0_WRPs_VAL(x)	\
 761    ((((x) >> ID_AA64DFR0_WRPs_SHIFT) & 0xf) + 1)
 762#define	ID_AA64DFR0_CTX_CMPs_SHIFT	28
 763#define	ID_AA64DFR0_CTX_CMPs_MASK	(UL(0xf) << ID_AA64DFR0_CTX_CMPs_SHIFT)
 764#define	ID_AA64DFR0_CTX_CMPs_VAL(x)	\
 765    ((((x) >> ID_AA64DFR0_CTX_CMPs_SHIFT) & 0xf) + 1)
 766#define	ID_AA64DFR0_PMSVer_SHIFT	32
 767#define	ID_AA64DFR0_PMSVer_MASK		(UL(0xf) << ID_AA64DFR0_PMSVer_SHIFT)
 768#define	ID_AA64DFR0_PMSVer_VAL(x)	((x) & ID_AA64DFR0_PMSVer_MASK)
 769#define	 ID_AA64DFR0_PMSVer_NONE	(UL(0x0) << ID_AA64DFR0_PMSVer_SHIFT)
 770#define	 ID_AA64DFR0_PMSVer_SPE		(UL(0x1) << ID_AA64DFR0_PMSVer_SHIFT)
 771#define	 ID_AA64DFR0_PMSVer_SPE_1_1	(UL(0x2) << ID_AA64DFR0_PMSVer_SHIFT)
 772#define	 ID_AA64DFR0_PMSVer_SPE_1_2	(UL(0x3) << ID_AA64DFR0_PMSVer_SHIFT)
 773#define	 ID_AA64DFR0_PMSVer_SPE_1_3	(UL(0x4) << ID_AA64DFR0_PMSVer_SHIFT)
 774#define	ID_AA64DFR0_DoubleLock_SHIFT	36
 775#define	ID_AA64DFR0_DoubleLock_MASK	(UL(0xf) << ID_AA64DFR0_DoubleLock_SHIFT)
 776#define	ID_AA64DFR0_DoubleLock_VAL(x)	((x) & ID_AA64DFR0_DoubleLock_MASK)
 777#define	 ID_AA64DFR0_DoubleLock_IMPL	(UL(0x0) << ID_AA64DFR0_DoubleLock_SHIFT)
 778#define	 ID_AA64DFR0_DoubleLock_NONE	(UL(0xf) << ID_AA64DFR0_DoubleLock_SHIFT)
 779#define	ID_AA64DFR0_TraceFilt_SHIFT	40
 780#define	ID_AA64DFR0_TraceFilt_MASK	(UL(0xf) << ID_AA64DFR0_TraceFilt_SHIFT)
 781#define	ID_AA64DFR0_TraceFilt_VAL(x)	((x) & ID_AA64DFR0_TraceFilt_MASK)
 782#define	 ID_AA64DFR0_TraceFilt_NONE	(UL(0x0) << ID_AA64DFR0_TraceFilt_SHIFT)
 783#define	 ID_AA64DFR0_TraceFilt_8_4	(UL(0x1) << ID_AA64DFR0_TraceFilt_SHIFT)
 784#define	ID_AA64DFR0_TraceBuffer_SHIFT	44
 785#define	ID_AA64DFR0_TraceBuffer_MASK	(UL(0xf) << ID_AA64DFR0_TraceBuffer_SHIFT)
 786#define	ID_AA64DFR0_TraceBuffer_VAL(x)	((x) & ID_AA64DFR0_TraceBuffer_MASK)
 787#define	 ID_AA64DFR0_TraceBuffer_NONE	(UL(0x0) << ID_AA64DFR0_TraceBuffer_SHIFT)
 788#define	 ID_AA64DFR0_TraceBuffer_IMPL	(UL(0x1) << ID_AA64DFR0_TraceBuffer_SHIFT)
 789#define	ID_AA64DFR0_MTPMU_SHIFT		48
 790#define	ID_AA64DFR0_MTPMU_MASK		(UL(0xf) << ID_AA64DFR0_MTPMU_SHIFT)
 791#define	ID_AA64DFR0_MTPMU_VAL(x)	((x) & ID_AA64DFR0_MTPMU_MASK)
 792#define	 ID_AA64DFR0_MTPMU_NONE		(UL(0x0) << ID_AA64DFR0_MTPMU_SHIFT)
 793#define	 ID_AA64DFR0_MTPMU_IMPL		(UL(0x1) << ID_AA64DFR0_MTPMU_SHIFT)
 794#define	 ID_AA64DFR0_MTPMU_NONE_MT_RES0	(UL(0xf) << ID_AA64DFR0_MTPMU_SHIFT)
 795#define	ID_AA64DFR0_BRBE_SHIFT		52
 796#define	ID_AA64DFR0_BRBE_MASK		(UL(0xf) << ID_AA64DFR0_BRBE_SHIFT)
 797#define	ID_AA64DFR0_BRBE_VAL(x)		((x) & ID_AA64DFR0_BRBE_MASK)
 798#define	 ID_AA64DFR0_BRBE_NONE		(UL(0x0) << ID_AA64DFR0_BRBE_SHIFT)
 799#define	 ID_AA64DFR0_BRBE_IMPL		(UL(0x1) << ID_AA64DFR0_BRBE_SHIFT)
 800#define	 ID_AA64DFR0_BRBE_EL3		(UL(0x2) << ID_AA64DFR0_BRBE_SHIFT)
 801#define	ID_AA64DFR0_HPMN0_SHIFT		60
 802#define	ID_AA64DFR0_HPMN0_MASK		(UL(0xf) << ID_AA64DFR0_HPMN0_SHIFT)
 803#define	ID_AA64DFR0_HPMN0_VAL(x)	((x) & ID_AA64DFR0_HPMN0_MASK)
 804#define	 ID_AA64DFR0_HPMN0_CONSTR	(UL(0x0) << ID_AA64DFR0_HPMN0_SHIFT)
 805#define	 ID_AA64DFR0_HPMN0_DEFINED	(UL(0x1) << ID_AA64DFR0_HPMN0_SHIFT)
 806
 807/* ID_AA64DFR1_EL1 */
 808#define	ID_AA64DFR1_EL1			MRS_REG(ID_AA64DFR1_EL1)
 809#define	ID_AA64DFR1_EL1_REG		MRS_REG_ALT_NAME(ID_AA64DFR1_EL1)
 810#define	ID_AA64DFR1_EL1_op0		3
 811#define	ID_AA64DFR1_EL1_op1		0
 812#define	ID_AA64DFR1_EL1_CRn		0
 813#define	ID_AA64DFR1_EL1_CRm		5
 814#define	ID_AA64DFR1_EL1_op2		1
 815
 816/* ID_AA64ISAR0_EL1 */
 817#define	ID_AA64ISAR0_EL1		MRS_REG(ID_AA64ISAR0_EL1)
 818#define	ID_AA64ISAR0_EL1_REG		MRS_REG_ALT_NAME(ID_AA64ISAR0_EL1)
 819#define	ID_AA64ISAR0_EL1_op0		3
 820#define	ID_AA64ISAR0_EL1_op1		0
 821#define	ID_AA64ISAR0_EL1_CRn		0
 822#define	ID_AA64ISAR0_EL1_CRm		6
 823#define	ID_AA64ISAR0_EL1_op2		0
 824#define	ID_AA64ISAR0_AES_SHIFT		4
 825#define	ID_AA64ISAR0_AES_MASK		(UL(0xf) << ID_AA64ISAR0_AES_SHIFT)
 826#define	ID_AA64ISAR0_AES_VAL(x)		((x) & ID_AA64ISAR0_AES_MASK)
 827#define	 ID_AA64ISAR0_AES_NONE		(UL(0x0) << ID_AA64ISAR0_AES_SHIFT)
 828#define	 ID_AA64ISAR0_AES_BASE		(UL(0x1) << ID_AA64ISAR0_AES_SHIFT)
 829#define	 ID_AA64ISAR0_AES_PMULL		(UL(0x2) << ID_AA64ISAR0_AES_SHIFT)
 830#define	ID_AA64ISAR0_SHA1_SHIFT		8
 831#define	ID_AA64ISAR0_SHA1_MASK		(UL(0xf) << ID_AA64ISAR0_SHA1_SHIFT)
 832#define	ID_AA64ISAR0_SHA1_VAL(x)	((x) & ID_AA64ISAR0_SHA1_MASK)
 833#define	 ID_AA64ISAR0_SHA1_NONE		(UL(0x0) << ID_AA64ISAR0_SHA1_SHIFT)
 834#define	 ID_AA64ISAR0_SHA1_BASE		(UL(0x1) << ID_AA64ISAR0_SHA1_SHIFT)
 835#define	ID_AA64ISAR0_SHA2_SHIFT		12
 836#define	ID_AA64ISAR0_SHA2_MASK		(UL(0xf) << ID_AA64ISAR0_SHA2_SHIFT)
 837#define	ID_AA64ISAR0_SHA2_VAL(x)	((x) & ID_AA64ISAR0_SHA2_MASK)
 838#define	 ID_AA64ISAR0_SHA2_NONE		(UL(0x0) << ID_AA64ISAR0_SHA2_SHIFT)
 839#define	 ID_AA64ISAR0_SHA2_BASE		(UL(0x1) << ID_AA64ISAR0_SHA2_SHIFT)
 840#define	 ID_AA64ISAR0_SHA2_512		(UL(0x2) << ID_AA64ISAR0_SHA2_SHIFT)
 841#define	ID_AA64ISAR0_CRC32_SHIFT	16
 842#define	ID_AA64ISAR0_CRC32_MASK		(UL(0xf) << ID_AA64ISAR0_CRC32_SHIFT)
 843#define	ID_AA64ISAR0_CRC32_VAL(x)	((x) & ID_AA64ISAR0_CRC32_MASK)
 844#define	 ID_AA64ISAR0_CRC32_NONE	(UL(0x0) << ID_AA64ISAR0_CRC32_SHIFT)
 845#define	 ID_AA64ISAR0_CRC32_BASE	(UL(0x1) << ID_AA64ISAR0_CRC32_SHIFT)
 846#define	ID_AA64ISAR0_Atomic_SHIFT	20
 847#define	ID_AA64ISAR0_Atomic_MASK	(UL(0xf) << ID_AA64ISAR0_Atomic_SHIFT)
 848#define	ID_AA64ISAR0_Atomic_VAL(x)	((x) & ID_AA64ISAR0_Atomic_MASK)
 849#define	 ID_AA64ISAR0_Atomic_NONE	(UL(0x0) << ID_AA64ISAR0_Atomic_SHIFT)
 850#define	 ID_AA64ISAR0_Atomic_IMPL	(UL(0x2) << ID_AA64ISAR0_Atomic_SHIFT)
 851#define	ID_AA64ISAR0_TME_SHIFT		24
 852#define	ID_AA64ISAR0_TME_MASK		(UL(0xf) << ID_AA64ISAR0_TME_SHIFT)
 853#define	 ID_AA64ISAR0_TME_NONE		(UL(0x0) << ID_AA64ISAR0_TME_SHIFT)
 854#define	 ID_AA64ISAR0_TME_IMPL		(UL(0x1) << ID_AA64ISAR0_TME_SHIFT)
 855#define	ID_AA64ISAR0_RDM_SHIFT		28
 856#define	ID_AA64ISAR0_RDM_MASK		(UL(0xf) << ID_AA64ISAR0_RDM_SHIFT)
 857#define	ID_AA64ISAR0_RDM_VAL(x)		((x) & ID_AA64ISAR0_RDM_MASK)
 858#define	 ID_AA64ISAR0_RDM_NONE		(UL(0x0) << ID_AA64ISAR0_RDM_SHIFT)
 859#define	 ID_AA64ISAR0_RDM_IMPL		(UL(0x1) << ID_AA64ISAR0_RDM_SHIFT)
 860#define	ID_AA64ISAR0_SHA3_SHIFT		32
 861#define	ID_AA64ISAR0_SHA3_MASK		(UL(0xf) << ID_AA64ISAR0_SHA3_SHIFT)
 862#define	ID_AA64ISAR0_SHA3_VAL(x)	((x) & ID_AA64ISAR0_SHA3_MASK)
 863#define	 ID_AA64ISAR0_SHA3_NONE		(UL(0x0) << ID_AA64ISAR0_SHA3_SHIFT)
 864#define	 ID_AA64ISAR0_SHA3_IMPL		(UL(0x1) << ID_AA64ISAR0_SHA3_SHIFT)
 865#define	ID_AA64ISAR0_SM3_SHIFT		36
 866#define	ID_AA64ISAR0_SM3_MASK		(UL(0xf) << ID_AA64ISAR0_SM3_SHIFT)
 867#define	ID_AA64ISAR0_SM3_VAL(x)		((x) & ID_AA64ISAR0_SM3_MASK)
 868#define	 ID_AA64ISAR0_SM3_NONE		(UL(0x0) << ID_AA64ISAR0_SM3_SHIFT)
 869#define	 ID_AA64ISAR0_SM3_IMPL		(UL(0x1) << ID_AA64ISAR0_SM3_SHIFT)
 870#define	ID_AA64ISAR0_SM4_SHIFT		40
 871#define	ID_AA64ISAR0_SM4_MASK		(UL(0xf) << ID_AA64ISAR0_SM4_SHIFT)
 872#define	ID_AA64ISAR0_SM4_VAL(x)		((x) & ID_AA64ISAR0_SM4_MASK)
 873#define	 ID_AA64ISAR0_SM4_NONE		(UL(0x0) << ID_AA64ISAR0_SM4_SHIFT)
 874#define	 ID_AA64ISAR0_SM4_IMPL		(UL(0x1) << ID_AA64ISAR0_SM4_SHIFT)
 875#define	ID_AA64ISAR0_DP_SHIFT		44
 876#define	ID_AA64ISAR0_DP_MASK		(UL(0xf) << ID_AA64ISAR0_DP_SHIFT)
 877#define	ID_AA64ISAR0_DP_VAL(x)		((x) & ID_AA64ISAR0_DP_MASK)
 878#define	 ID_AA64ISAR0_DP_NONE		(UL(0x0) << ID_AA64ISAR0_DP_SHIFT)
 879#define	 ID_AA64ISAR0_DP_IMPL		(UL(0x1) << ID_AA64ISAR0_DP_SHIFT)
 880#define	ID_AA64ISAR0_FHM_SHIFT		48
 881#define	ID_AA64ISAR0_FHM_MASK		(UL(0xf) << ID_AA64ISAR0_FHM_SHIFT)
 882#define	ID_AA64ISAR0_FHM_VAL(x)		((x) & ID_AA64ISAR0_FHM_MASK)
 883#define	 ID_AA64ISAR0_FHM_NONE		(UL(0x0) << ID_AA64ISAR0_FHM_SHIFT)
 884#define	 ID_AA64ISAR0_FHM_IMPL		(UL(0x1) << ID_AA64ISAR0_FHM_SHIFT)
 885#define	ID_AA64ISAR0_TS_SHIFT		52
 886#define	ID_AA64ISAR0_TS_MASK		(UL(0xf) << ID_AA64ISAR0_TS_SHIFT)
 887#define	ID_AA64ISAR0_TS_VAL(x)		((x) & ID_AA64ISAR0_TS_MASK)
 888#define	 ID_AA64ISAR0_TS_NONE		(UL(0x0) << ID_AA64ISAR0_TS_SHIFT)
 889#define	 ID_AA64ISAR0_TS_CondM_8_4	(UL(0x1) << ID_AA64ISAR0_TS_SHIFT)
 890#define	 ID_AA64ISAR0_TS_CondM_8_5	(UL(0x2) << ID_AA64ISAR0_TS_SHIFT)
 891#define	ID_AA64ISAR0_TLB_SHIFT		56
 892#define	ID_AA64ISAR0_TLB_MASK		(UL(0xf) << ID_AA64ISAR0_TLB_SHIFT)
 893#define	ID_AA64ISAR0_TLB_VAL(x)		((x) & ID_AA64ISAR0_TLB_MASK)
 894#define	 ID_AA64ISAR0_TLB_NONE		(UL(0x0) << ID_AA64ISAR0_TLB_SHIFT)
 895#define	 ID_AA64ISAR0_TLB_TLBIOS	(UL(0x1) << ID_AA64ISAR0_TLB_SHIFT)
 896#define	 ID_AA64ISAR0_TLB_TLBIOSR	(UL(0x2) << ID_AA64ISAR0_TLB_SHIFT)
 897#define	ID_AA64ISAR0_RNDR_SHIFT		60
 898#define	ID_AA64ISAR0_RNDR_MASK		(UL(0xf) << ID_AA64ISAR0_RNDR_SHIFT)
 899#define	ID_AA64ISAR0_RNDR_VAL(x)	((x) & ID_AA64ISAR0_RNDR_MASK)
 900#define	 ID_AA64ISAR0_RNDR_NONE		(UL(0x0) << ID_AA64ISAR0_RNDR_SHIFT)
 901#define	 ID_AA64ISAR0_RNDR_IMPL		(UL(0x1) << ID_AA64ISAR0_RNDR_SHIFT)
 902
 903/* ID_AA64ISAR1_EL1 */
 904#define	ID_AA64ISAR1_EL1		MRS_REG(ID_AA64ISAR1_EL1)
 905#define	ID_AA64ISAR1_EL1_REG		MRS_REG_ALT_NAME(ID_AA64ISAR1_EL1)
 906#define	ID_AA64ISAR1_EL1_op0		3
 907#define	ID_AA64ISAR1_EL1_op1		0
 908#define	ID_AA64ISAR1_EL1_CRn		0
 909#define	ID_AA64ISAR1_EL1_CRm		6
 910#define	ID_AA64ISAR1_EL1_op2		1
 911#define	ID_AA64ISAR1_DPB_SHIFT		0
 912#define	ID_AA64ISAR1_DPB_MASK		(UL(0xf) << ID_AA64ISAR1_DPB_SHIFT)
 913#define	ID_AA64ISAR1_DPB_VAL(x)		((x) & ID_AA64ISAR1_DPB_MASK)
 914#define	 ID_AA64ISAR1_DPB_NONE		(UL(0x0) << ID_AA64ISAR1_DPB_SHIFT)
 915#define	 ID_AA64ISAR1_DPB_DCCVAP	(UL(0x1) << ID_AA64ISAR1_DPB_SHIFT)
 916#define	 ID_AA64ISAR1_DPB_DCCVADP	(UL(0x2) << ID_AA64ISAR1_DPB_SHIFT)
 917#define	ID_AA64ISAR1_APA_SHIFT		4
 918#define	ID_AA64ISAR1_APA_MASK		(UL(0xf) << ID_AA64ISAR1_APA_SHIFT)
 919#define	ID_AA64ISAR1_APA_VAL(x)		((x) & ID_AA64ISAR1_APA_MASK)
 920#define	 ID_AA64ISAR1_APA_NONE		(UL(0x0) << ID_AA64ISAR1_APA_SHIFT)
 921#define	 ID_AA64ISAR1_APA_PAC		(UL(0x1) << ID_AA64ISAR1_APA_SHIFT)
 922#define	 ID_AA64ISAR1_APA_EPAC		(UL(0x2) << ID_AA64ISAR1_APA_SHIFT)
 923#define	 ID_AA64ISAR1_APA_EPAC2		(UL(0x3) << ID_AA64ISAR1_APA_SHIFT)
 924#define	 ID_AA64ISAR1_APA_FPAC		(UL(0x4) << ID_AA64ISAR1_APA_SHIFT)
 925#define	 ID_AA64ISAR1_APA_FPAC_COMBINED	(UL(0x5) << ID_AA64ISAR1_APA_SHIFT)
 926#define	ID_AA64ISAR1_API_SHIFT		8
 927#define	ID_AA64ISAR1_API_MASK		(UL(0xf) << ID_AA64ISAR1_API_SHIFT)
 928#define	ID_AA64ISAR1_API_VAL(x)		((x) & ID_AA64ISAR1_API_MASK)
 929#define	 ID_AA64ISAR1_API_NONE		(UL(0x0) << ID_AA64ISAR1_API_SHIFT)
 930#define	 ID_AA64ISAR1_API_PAC		(UL(0x1) << ID_AA64ISAR1_API_SHIFT)
 931#define	 ID_AA64ISAR1_API_EPAC		(UL(0x2) << ID_AA64ISAR1_API_SHIFT)
 932#define	 ID_AA64ISAR1_API_EPAC2		(UL(0x3) << ID_AA64ISAR1_API_SHIFT)
 933#define	 ID_AA64ISAR1_API_FPAC		(UL(0x4) << ID_AA64ISAR1_API_SHIFT)
 934#define	 ID_AA64ISAR1_API_FPAC_COMBINED	(UL(0x5) << ID_AA64ISAR1_API_SHIFT)
 935#define	ID_AA64ISAR1_JSCVT_SHIFT	12
 936#define	ID_AA64ISAR1_JSCVT_MASK		(UL(0xf) << ID_AA64ISAR1_JSCVT_SHIFT)
 937#define	ID_AA64ISAR1_JSCVT_VAL(x)	((x) & ID_AA64ISAR1_JSCVT_MASK)
 938#define	 ID_AA64ISAR1_JSCVT_NONE	(UL(0x0) << ID_AA64ISAR1_JSCVT_SHIFT)
 939#define	 ID_AA64ISAR1_JSCVT_IMPL	(UL(0x1) << ID_AA64ISAR1_JSCVT_SHIFT)
 940#define	ID_AA64ISAR1_FCMA_SHIFT		16
 941#define	ID_AA64ISAR1_FCMA_MASK		(UL(0xf) << ID_AA64ISAR1_FCMA_SHIFT)
 942#define	ID_AA64ISAR1_FCMA_VAL(x)	((x) & ID_AA64ISAR1_FCMA_MASK)
 943#define	 ID_AA64ISAR1_FCMA_NONE		(UL(0x0) << ID_AA64ISAR1_FCMA_SHIFT)
 944#define	 ID_AA64ISAR1_FCMA_IMPL		(UL(0x1) << ID_AA64ISAR1_FCMA_SHIFT)
 945#define	ID_AA64ISAR1_LRCPC_SHIFT	20
 946#define	ID_AA64ISAR1_LRCPC_MASK		(UL(0xf) << ID_AA64ISAR1_LRCPC_SHIFT)
 947#define	ID_AA64ISAR1_LRCPC_VAL(x)	((x) & ID_AA64ISAR1_LRCPC_MASK)
 948#define	 ID_AA64ISAR1_LRCPC_NONE	(UL(0x0) << ID_AA64ISAR1_LRCPC_SHIFT)
 949#define	 ID_AA64ISAR1_LRCPC_RCPC_8_3	(UL(0x1) << ID_AA64ISAR1_LRCPC_SHIFT)
 950#define	 ID_AA64ISAR1_LRCPC_RCPC_8_4	(UL(0x2) << ID_AA64ISAR1_LRCPC_SHIFT)
 951#define	ID_AA64ISAR1_GPA_SHIFT		24
 952#define	ID_AA64ISAR1_GPA_MASK		(UL(0xf) << ID_AA64ISAR1_GPA_SHIFT)
 953#define	ID_AA64ISAR1_GPA_VAL(x)		((x) & ID_AA64ISAR1_GPA_MASK)
 954#define	 ID_AA64ISAR1_GPA_NONE		(UL(0x0) << ID_AA64ISAR1_GPA_SHIFT)
 955#define	 ID_AA64ISAR1_GPA_IMPL		(UL(0x1) << ID_AA64ISAR1_GPA_SHIFT)
 956#define	ID_AA64ISAR1_GPI_SHIFT		28
 957#define	ID_AA64ISAR1_GPI_MASK		(UL(0xf) << ID_AA64ISAR1_GPI_SHIFT)
 958#define	ID_AA64ISAR1_GPI_VAL(x)		((x) & ID_AA64ISAR1_GPI_MASK)
 959#define	 ID_AA64ISAR1_GPI_NONE		(UL(0x0) << ID_AA64ISAR1_GPI_SHIFT)
 960#define	 ID_AA64ISAR1_GPI_IMPL		(UL(0x1) << ID_AA64ISAR1_GPI_SHIFT)
 961#define	ID_AA64ISAR1_FRINTTS_SHIFT	32
 962#define	ID_AA64ISAR1_FRINTTS_MASK	(UL(0xf) << ID_AA64ISAR1_FRINTTS_SHIFT)
 963#define	ID_AA64ISAR1_FRINTTS_VAL(x)	((x) & ID_AA64ISAR1_FRINTTS_MASK)
 964#define	 ID_AA64ISAR1_FRINTTS_NONE	(UL(0x0) << ID_AA64ISAR1_FRINTTS_SHIFT)
 965#define	 ID_AA64ISAR1_FRINTTS_IMPL	(UL(0x1) << ID_AA64ISAR1_FRINTTS_SHIFT)
 966#define	ID_AA64ISAR1_SB_SHIFT		36
 967#define	ID_AA64ISAR1_SB_MASK		(UL(0xf) << ID_AA64ISAR1_SB_SHIFT)
 968#define	ID_AA64ISAR1_SB_VAL(x)		((x) & ID_AA64ISAR1_SB_MASK)
 969#define	 ID_AA64ISAR1_SB_NONE		(UL(0x0) << ID_AA64ISAR1_SB_SHIFT)
 970#define	 ID_AA64ISAR1_SB_IMPL		(UL(0x1) << ID_AA64ISAR1_SB_SHIFT)
 971#define	ID_AA64ISAR1_SPECRES_SHIFT	40
 972#define	ID_AA64ISAR1_SPECRES_MASK	(UL(0xf) << ID_AA64ISAR1_SPECRES_SHIFT)
 973#define	ID_AA64ISAR1_SPECRES_VAL(x)	((x) & ID_AA64ISAR1_SPECRES_MASK)
 974#define	 ID_AA64ISAR1_SPECRES_NONE	(UL(0x0) << ID_AA64ISAR1_SPECRES_SHIFT)
 975#define	 ID_AA64ISAR1_SPECRES_IMPL	(UL(0x1) << ID_AA64ISAR1_SPECRES_SHIFT)
 976#define	ID_AA64ISAR1_BF16_SHIFT		44
 977#define	ID_AA64ISAR1_BF16_MASK		(UL(0xf) << ID_AA64ISAR1_BF16_SHIFT)
 978#define	ID_AA64ISAR1_BF16_VAL(x)	((x) & ID_AA64ISAR1_BF16_MASK)
 979#define	 ID_AA64ISAR1_BF16_NONE		(UL(0x0) << ID_AA64ISAR1_BF16_SHIFT)
 980#define	 ID_AA64ISAR1_BF16_IMPL		(UL(0x1) << ID_AA64ISAR1_BF16_SHIFT)
 981#define	 ID_AA64ISAR1_BF16_EBF		(UL(0x2) << ID_AA64ISAR1_BF16_SHIFT)
 982#define	ID_AA64ISAR1_DGH_SHIFT		48
 983#define	ID_AA64ISAR1_DGH_MASK		(UL(0xf) << ID_AA64ISAR1_DGH_SHIFT)
 984#define	ID_AA64ISAR1_DGH_VAL(x)		((x) & ID_AA64ISAR1_DGH_MASK)
 985#define	 ID_AA64ISAR1_DGH_NONE		(UL(0x0) << ID_AA64ISAR1_DGH_SHIFT)
 986#define	 ID_AA64ISAR1_DGH_IMPL		(UL(0x1) << ID_AA64ISAR1_DGH_SHIFT)
 987#define	ID_AA64ISAR1_I8MM_SHIFT		52
 988#define	ID_AA64ISAR1_I8MM_MASK		(UL(0xf) << ID_AA64ISAR1_I8MM_SHIFT)
 989#define	ID_AA64ISAR1_I8MM_VAL(x)	((x) & ID_AA64ISAR1_I8MM_MASK)
 990#define	 ID_AA64ISAR1_I8MM_NONE		(UL(0x0) << ID_AA64ISAR1_I8MM_SHIFT)
 991#define	 ID_AA64ISAR1_I8MM_IMPL		(UL(0x1) << ID_AA64ISAR1_I8MM_SHIFT)
 992#define	ID_AA64ISAR1_XS_SHIFT		56
 993#define	ID_AA64ISAR1_XS_MASK		(UL(0xf) << ID_AA64ISAR1_XS_SHIFT)
 994#define	ID_AA64ISAR1_XS_VAL(x)		((x) & ID_AA64ISAR1_XS_MASK)
 995#define	 ID_AA64ISAR1_XS_NONE		(UL(0x0) << ID_AA64ISAR1_XS_SHIFT)
 996#define	 ID_AA64ISAR1_XS_IMPL		(UL(0x1) << ID_AA64ISAR1_XS_SHIFT)
 997#define	ID_AA64ISAR1_LS64_SHIFT		60
 998#define	ID_AA64ISAR1_LS64_MASK		(UL(0xf) << ID_AA64ISAR1_LS64_SHIFT)
 999#define	ID_AA64ISAR1_LS64_VAL(x)	((x) & ID_AA64ISAR1_LS64_MASK)
1000#define	 ID_AA64ISAR1_LS64_NONE		(UL(0x0) << ID_AA64ISAR1_LS64_SHIFT)
1001#define	 ID_AA64ISAR1_LS64_IMPL		(UL(0x1) << ID_AA64ISAR1_LS64_SHIFT)
1002#define	 ID_AA64ISAR1_LS64_V		(UL(0x2) << ID_AA64ISAR1_LS64_SHIFT)
1003#define	 ID_AA64ISAR1_LS64_ACCDATA	(UL(0x3) << ID_AA64ISAR1_LS64_SHIFT)
1004
1005/* ID_AA64ISAR2_EL1 */
1006#define	ID_AA64ISAR2_EL1		MRS_REG(ID_AA64ISAR2_EL1)
1007#define	ID_AA64ISAR2_EL1_REG		MRS_REG_ALT_NAME(ID_AA64ISAR2_EL1)
1008#define	ID_AA64ISAR2_EL1_op0		3
1009#define	ID_AA64ISAR2_EL1_op1		0
1010#define	ID_AA64ISAR2_EL1_CRn		0
1011#define	ID_AA64ISAR2_EL1_CRm		6
1012#define	ID_AA64ISAR2_EL1_op2		2
1013#define	ID_AA64ISAR2_WFxT_SHIFT		0
1014#define	ID_AA64ISAR2_WFxT_MASK		(UL(0xf) << ID_AA64ISAR2_WFxT_SHIFT)
1015#define	ID_AA64ISAR2_WFxT_VAL(x)	((x) & ID_AA64ISAR2_WFxT_MASK)
1016#define	 ID_AA64ISAR2_WFxT_NONE		(UL(0x0) << ID_AA64ISAR2_WFxT_SHIFT)
1017#define	 ID_AA64ISAR2_WFxT_IMPL		(UL(0x1) << ID_AA64ISAR2_WFxT_SHIFT)
1018#define	ID_AA64ISAR2_RPRES_SHIFT	4
1019#define	ID_AA64ISAR2_RPRES_MASK		(UL(0xf) << ID_AA64ISAR2_RPRES_SHIFT)
1020#define	ID_AA64ISAR2_RPRES_VAL(x)	((x) & ID_AA64ISAR2_RPRES_MASK)
1021#define	 ID_AA64ISAR2_RPRES_NONE	(UL(0x0) << ID_AA64ISAR2_RPRES_SHIFT)
1022#define	 ID_AA64ISAR2_RPRES_IMPL	(UL(0x1) << ID_AA64ISAR2_RPRES_SHIFT)
1023#define	ID_AA64ISAR2_GPA3_SHIFT		8
1024#define	ID_AA64ISAR2_GPA3_MASK		(UL(0xf) << ID_AA64ISAR2_GPA3_SHIFT)
1025#define	ID_AA64ISAR2_GPA3_VAL(x)	((x) & ID_AA64ISAR2_GPA3_MASK)
1026#define	 ID_AA64ISAR2_GPA3_NONE		(UL(0x0) << ID_AA64ISAR2_GPA3_SHIFT)
1027#define	 ID_AA64ISAR2_GPA3_IMPL		(UL(0x1) << ID_AA64ISAR2_GPA3_SHIFT)
1028#define	ID_AA64ISAR2_APA3_SHIFT		12
1029#define	ID_AA64ISAR2_APA3_MASK		(UL(0xf) << ID_AA64ISAR2_APA3_SHIFT)
1030#define	ID_AA64ISAR2_APA3_VAL(x)	((x) & ID_AA64ISAR2_APA3_MASK)
1031#define	 ID_AA64ISAR2_APA3_NONE		(UL(0x0) << ID_AA64ISAR2_APA3_SHIFT)
1032#define	 ID_AA64ISAR2_APA3_PAC		(UL(0x1) << ID_AA64ISAR2_APA3_SHIFT)
1033#define	 ID_AA64ISAR2_APA3_EPAC		(UL(0x2) << ID_AA64ISAR2_APA3_SHIFT)
1034#define	 ID_AA64ISAR2_APA3_EPAC2	(UL(0x3) << ID_AA64ISAR2_APA3_SHIFT)
1035#define	 ID_AA64ISAR2_APA3_FPAC		(UL(0x4) << ID_AA64ISAR2_APA3_SHIFT)
1036#define	 ID_AA64ISAR2_APA3_FPAC_COMBINED (UL(0x5) << ID_AA64ISAR2_APA3_SHIFT)
1037#define	ID_AA64ISAR2_MOPS_SHIFT		16
1038#define	ID_AA64ISAR2_MOPS_MASK		(UL(0xf) << ID_AA64ISAR2_MOPS_SHIFT)
1039#define	ID_AA64ISAR2_MOPS_VAL(x)	((x) & ID_AA64ISAR2_MOPS_MASK)
1040#define	 ID_AA64ISAR2_MOPS_NONE		(UL(0x0) << ID_AA64ISAR2_MOPS_SHIFT)
1041#define	 ID_AA64ISAR2_MOPS_IMPL		(UL(0x1) << ID_AA64ISAR2_MOPS_SHIFT)
1042#define	ID_AA64ISAR2_BC_SHIFT		20
1043#define	ID_AA64ISAR2_BC_MASK		(UL(0xf) << ID_AA64ISAR2_BC_SHIFT)
1044#define	ID_AA64ISAR2_BC_VAL(x)		((x) & ID_AA64ISAR2_BC_MASK)
1045#define	 ID_AA64ISAR2_BC_NONE		(UL(0x0) << ID_AA64ISAR2_BC_SHIFT)
1046#define	 ID_AA64ISAR2_BC_IMPL		(UL(0x1) << ID_AA64ISAR2_BC_SHIFT)
1047#define	ID_AA64ISAR2_PAC_frac_SHIFT	28
1048#define	ID_AA64ISAR2_PAC_frac_MASK	(UL(0xf) << ID_AA64ISAR2_PAC_frac_SHIFT)
1049#define	ID_AA64ISAR2_PAC_frac_VAL(x)	((x) & ID_AA64ISAR2_PAC_frac_MASK)
1050#define	 ID_AA64ISAR2_PAC_frac_NONE	(UL(0x0) << ID_AA64ISAR2_PAC_frac_SHIFT)
1051#define	 ID_AA64ISAR2_PAC_frac_IMPL	(UL(0x1) << ID_AA64ISAR2_PAC_frac_SHIFT)
1052
1053/* ID_AA64MMFR0_EL1 */
1054#define	ID_AA64MMFR0_EL1		MRS_REG(ID_AA64MMFR0_EL1)
1055#define	ID_AA64MMFR0_EL1_REG		MRS_REG_ALT_NAME(ID_AA64MMFR0_EL1)
1056#define	ID_AA64MMFR0_EL1_op0		3
1057#define	ID_AA64MMFR0_EL1_op1		0
1058#define	ID_AA64MMFR0_EL1_CRn		0
1059#define	ID_AA64MMFR0_EL1_CRm		7
1060#define	ID_AA64MMFR0_EL1_op2		0
1061#define	ID_AA64MMFR0_PARange_SHIFT	0
1062#define	ID_AA64MMFR0_PARange_MASK	(UL(0xf) << ID_AA64MMFR0_PARange_SHIFT)
1063#define	ID_AA64MMFR0_PARange_VAL(x)	((x) & ID_AA64MMFR0_PARange_MASK)
1064#define	 ID_AA64MMFR0_PARange_4G	(UL(0x0) << ID_AA64MMFR0_PARange_SHIFT)
1065#define	 ID_AA64MMFR0_PARange_64G	(UL(0x1) << ID_AA64MMFR0_PARange_SHIFT)
1066#define	 ID_AA64MMFR0_PARange_1T	(UL(0x2) << ID_AA64MMFR0_PARange_SHIFT)
1067#define	 ID_AA64MMFR0_PARange_4T	(UL(0x3) << ID_AA64MMFR0_PARange_SHIFT)
1068#define	 ID_AA64MMFR0_PARange_16T	(UL(0x4) << ID_AA64MMFR0_PARange_SHIFT)
1069#define	 ID_AA64MMFR0_PARange_256T	(UL(0x5) << ID_AA64MMFR0_PARange_SHIFT)
1070#define	 ID_AA64MMFR0_PARange_4P	(UL(0x6) << ID_AA64MMFR0_PARange_SHIFT)
1071#define	ID_AA64MMFR0_ASIDBits_SHIFT	4
1072#define	ID_AA64MMFR0_ASIDBits_MASK	(UL(0xf) << ID_AA64MMFR0_ASIDBits_SHIFT)
1073#define	ID_AA64MMFR0_ASIDBits_VAL(x)	((x) & ID_AA64MMFR0_ASIDBits_MASK)
1074#define	 ID_AA64MMFR0_ASIDBits_8	(UL(0x0) << ID_AA64MMFR0_ASIDBits_SHIFT)
1075#define	 ID_AA64MMFR0_ASIDBits_16	(UL(0x2) << ID_AA64MMFR0_ASIDBits_SHIFT)
1076#define	ID_AA64MMFR0_BigEnd_SHIFT	8
1077#define	ID_AA64MMFR0_BigEnd_MASK	(UL(0xf) << ID_AA64MMFR0_BigEnd_SHIFT)
1078#define	ID_AA64MMFR0_BigEnd_VAL(x)	((x) & ID_AA64MMFR0_BigEnd_MASK)
1079#define	 ID_AA64MMFR0_BigEnd_FIXED	(UL(0x0) << ID_AA64MMFR0_BigEnd_SHIFT)
1080#define	 ID_AA64MMFR0_BigEnd_MIXED	(UL(0x1) << ID_AA64MMFR0_BigEnd_SHIFT)
1081#define	ID_AA64MMFR0_SNSMem_SHIFT	12
1082#define	ID_AA64MMFR0_SNSMem_MASK	(UL(0xf) << ID_AA64MMFR0_SNSMem_SHIFT)
1083#define	ID_AA64MMFR0_SNSMem_VAL(x)	((x) & ID_AA64MMFR0_SNSMem_MASK)
1084#define	 ID_AA64MMFR0_SNSMem_NONE	(UL(0x0) << ID_AA64MMFR0_SNSMem_SHIFT)
1085#define	 ID_AA64MMFR0_SNSMem_DISTINCT	(UL(0x1) << ID_AA64MMFR0_SNSMem_SHIFT)
1086#define	ID_AA64MMFR0_BigEndEL0_SHIFT	16
1087#define	ID_AA64MMFR0_BigEndEL0_MASK	(UL(0xf) << ID_AA64MMFR0_BigEndEL0_SHIFT)
1088#define	ID_AA64MMFR0_BigEndEL0_VAL(x)	((x) & ID_AA64MMFR0_BigEndEL0_MASK)
1089#define	 ID_AA64MMFR0_BigEndEL0_FIXED	(UL(0x0) << ID_AA64MMFR0_BigEndEL0_SHIFT)
1090#define	 ID_AA64MMFR0_BigEndEL0_MIXED	(UL(0x1) << ID_AA64MMFR0_BigEndEL0_SHIFT)
1091#define	ID_AA64MMFR0_TGran16_SHIFT	20
1092#define	ID_AA64MMFR0_TGran16_MASK	(UL(0xf) << ID_AA64MMFR0_TGran16_SHIFT)
1093#define	ID_AA64MMFR0_TGran16_VAL(x)	((x) & ID_AA64MMFR0_TGran16_MASK)
1094#define	 ID_AA64MMFR0_TGran16_NONE	(UL(0x0) << ID_AA64MMFR0_TGran16_SHIFT)
1095#define	 ID_AA64MMFR0_TGran16_IMPL	(UL(0x1) << ID_AA64MMFR0_TGran16_SHIFT)
1096#define	 ID_AA64MMFR0_TGran16_LPA2	(UL(0x2) << ID_AA64MMFR0_TGran16_SHIFT)
1097#define	ID_AA64MMFR0_TGran64_SHIFT	24
1098#define	ID_AA64MMFR0_TGran64_MASK	(UL(0xf) << ID_AA64MMFR0_TGran64_SHIFT)
1099#define	ID_AA64MMFR0_TGran64_VAL(x)	((x) & ID_AA64MMFR0_TGran64_MASK)
1100#define	 ID_AA64MMFR0_TGran64_IMPL	(UL(0x0) << ID_AA64MMFR0_TGran64_SHIFT)
1101#define	 ID_AA64MMFR0_TGran64_NONE	(UL(0xf) << ID_AA64MMFR0_TGran64_SHIFT)
1102#define	ID_AA64MMFR0_TGran4_SHIFT	28
1103#define	ID_AA64MMFR0_TGran4_MASK	(UL(0xf) << ID_AA64MMFR0_TGran4_SHIFT)
1104#define	ID_AA64MMFR0_TGran4_VAL(x)	((x) & ID_AA64MMFR0_TGran4_MASK)
1105#define	 ID_AA64MMFR0_TGran4_IMPL	(UL(0x0) << ID_AA64MMFR0_TGran4_SHIFT)
1106#define	 ID_AA64MMFR0_TGran4_LPA2	(UL(0x1) << ID_AA64MMFR0_TGran4_SHIFT)
1107#define	 ID_AA64MMFR0_TGran4_NONE	(UL(0xf) << ID_AA64MMFR0_TGran4_SHIFT)
1108#define	ID_AA64MMFR0_TGran16_2_SHIFT	32
1109#define	ID_AA64MMFR0_TGran16_2_MASK	(UL(0xf) << ID_AA64MMFR0_TGran16_2_SHIFT)
1110#define	ID_AA64MMFR0_TGran16_2_VAL(x)	((x) & ID_AA64MMFR0_TGran16_2_MASK)
1111#define	 ID_AA64MMFR0_TGran16_2_TGran16	(UL(0x0) << ID_AA64MMFR0_TGran16_2_SHIFT)
1112#define	 ID_AA64MMFR0_TGran16_2_NONE	(UL(0x1) << ID_AA64MMFR0_TGran16_2_SHIFT)
1113#define	 ID_AA64MMFR0_TGran16_2_IMPL	(UL(0x2) << ID_AA64MMFR0_TGran16_2_SHIFT)
1114#define	 ID_AA64MMFR0_TGran16_2_LPA2	(UL(0x3) << ID_AA64MMFR0_TGran16_2_SHIFT)
1115#define	ID_AA64MMFR0_TGran64_2_SHIFT	36
1116#define	ID_AA64MMFR0_TGran64_2_MASK	(UL(0xf) << ID_AA64MMFR0_TGran64_2_SHIFT)
1117#define	ID_AA64MMFR0_TGran64_2_VAL(x)	((x) & ID_AA64MMFR0_TGran64_2_MASK)
1118#define	 ID_AA64MMFR0_TGran64_2_TGran64	(UL(0x0) << ID_AA64MMFR0_TGran64_2_SHIFT)
1119#define	 ID_AA64MMFR0_TGran64_2_NONE	(UL(0x1) << ID_AA64MMFR0_TGran64_2_SHIFT)
1120#define	 ID_AA64MMFR0_TGran64_2_IMPL	(UL(0x2) << ID_AA64MMFR0_TGran64_2_SHIFT)
1121#define	ID_AA64MMFR0_TGran4_2_SHIFT	40
1122#define	ID_AA64MMFR0_TGran4_2_MASK	(UL(0xf) << ID_AA64MMFR0_TGran4_2_SHIFT)
1123#define	ID_AA64MMFR0_TGran4_2_VAL(x)	((x) & ID_AA64MMFR0_TGran4_2_MASK)
1124#define	 ID_AA64MMFR0_TGran4_2_TGran4	(UL(0x0) << ID_AA64MMFR0_TGran4_2_SHIFT)
1125#define	 ID_AA64MMFR0_TGran4_2_NONE	(UL(0x1) << ID_AA64MMFR0_TGran4_2_SHIFT)
1126#define	 ID_AA64MMFR0_TGran4_2_IMPL	(UL(0x2) << ID_AA64MMFR0_TGran4_2_SHIFT)
1127#define	 ID_AA64MMFR0_TGran4_2_LPA2	(UL(0x3) << ID_AA64MMFR0_TGran4_2_SHIFT)
1128#define	ID_AA64MMFR0_ExS_SHIFT		44
1129#define	ID_AA64MMFR0_ExS_MASK		(UL(0xf) << ID_AA64MMFR0_ExS_SHIFT)
1130#define	ID_AA64MMFR0_ExS_VAL(x)		((x) & ID_AA64MMFR0_ExS_MASK)
1131#define	 ID_AA64MMFR0_ExS_ALL		(UL(0x0) << ID_AA64MMFR0_ExS_SHIFT)
1132#define	 ID_AA64MMFR0_ExS_IMPL		(UL(0x1) << ID_AA64MMFR0_ExS_SHIFT)
1133#define	ID_AA64MMFR0_FGT_SHIFT		56
1134#define	ID_AA64MMFR0_FGT_MASK		(UL(0xf) << ID_AA64MMFR0_FGT_SHIFT)
1135#define	ID_AA64MMFR0_FGT_VAL(x)		((x) & ID_AA64MMFR0_FGT_MASK)
1136#define	 ID_AA64MMFR0_FGT_NONE		(UL(0x0) << ID_AA64MMFR0_FGT_SHIFT)
1137#define	 ID_AA64MMFR0_FGT_IMPL		(UL(0x1) << ID_AA64MMFR0_FGT_SHIFT)
1138#define	ID_AA64MMFR0_ECV_SHIFT		60
1139#define	ID_AA64MMFR0_ECV_MASK		(UL(0xf) << ID_AA64MMFR0_ECV_SHIFT)
1140#define	ID_AA64MMFR0_ECV_VAL(x)		((x) & ID_AA64MMFR0_ECV_MASK)
1141#define	 ID_AA64MMFR0_ECV_NONE		(UL(0x0) << ID_AA64MMFR0_ECV_SHIFT)
1142#define	 ID_AA64MMFR0_ECV_IMPL		(UL(0x1) << ID_AA64MMFR0_ECV_SHIFT)
1143#define	 ID_AA64MMFR0_ECV_CNTHCTL	(UL(0x2) << ID_AA64MMFR0_ECV_SHIFT)
1144
1145/* ID_AA64MMFR1_EL1 */
1146#define	ID_AA64MMFR1_EL1		MRS_REG(ID_AA64MMFR1_EL1)
1147#define	ID_AA64MMFR1_EL1_REG		MRS_REG_ALT_NAME(ID_AA64MMFR1_EL1)
1148#define	ID_AA64MMFR1_EL1_op0		3
1149#define	ID_AA64MMFR1_EL1_op1		0
1150#define	ID_AA64MMFR1_EL1_CRn		0
1151#define	ID_AA64MMFR1_EL1_CRm		7
1152#define	ID_AA64MMFR1_EL1_op2		1
1153#define	ID_AA64MMFR1_HAFDBS_SHIFT	0
1154#define	ID_AA64MMFR1_HAFDBS_MASK	(UL(0xf) << ID_AA64MMFR1_HAFDBS_SHIFT)
1155#define	ID_AA64MMFR1_HAFDBS_VAL(x)	((x) & ID_AA64MMFR1_HAFDBS_MASK)
1156#define	 ID_AA64MMFR1_HAFDBS_NONE	(UL(0x0) << ID_AA64MMFR1_HAFDBS_SHIFT)
1157#define	 ID_AA64MMFR1_HAFDBS_AF		(UL(0x1) << ID_AA64MMFR1_HAFDBS_SHIFT)
1158#define	 ID_AA64MMFR1_HAFDBS_AF_DBS	(UL(0x2) << ID_AA64MMFR1_HAFDBS_SHIFT)
1159#define	ID_AA64MMFR1_VMIDBits_SHIFT	4
1160#define	ID_AA64MMFR1_VMIDBits_MASK	(UL(0xf) << ID_AA64MMFR1_VMIDBits_SHIFT)
1161#define	ID_AA64MMFR1_VMIDBits_VAL(x)	((x) & ID_AA64MMFR1_VMIDBits_MASK)
1162#define	 ID_AA64MMFR1_VMIDBits_8	(UL(0x0) << ID_AA64MMFR1_VMIDBits_SHIFT)
1163#define	 ID_AA64MMFR1_VMIDBits_16	(UL(0x2) << ID_AA64MMFR1_VMIDBits_SHIFT)
1164#define	ID_AA64MMFR1_VH_SHIFT		8
1165#define	ID_AA64MMFR1_VH_MASK		(UL(0xf) << ID_AA64MMFR1_VH_SHIFT)
1166#define	ID_AA64MMFR1_VH_VAL(x)		((x) & ID_AA64MMFR1_VH_MASK)
1167#define	 ID_AA64MMFR1_VH_NONE		(UL(0x0) << ID_AA64MMFR1_VH_SHIFT)
1168#define	 ID_AA64MMFR1_VH_IMPL		(UL(0x1) << ID_AA64MMFR1_VH_SHIFT)
1169#define	ID_AA64MMFR1_HPDS_SHIFT		12
1170#define	ID_AA64MMFR1_HPDS_MASK		(UL(0xf) << ID_AA64MMFR1_HPDS_SHIFT)
1171#define	ID_AA64MMFR1_HPDS_VAL(x)	((x) & ID_AA64MMFR1_HPDS_MASK)
1172#define	 ID_AA64MMFR1_HPDS_NONE		(UL(0x0) << ID_AA64MMFR1_HPDS_SHIFT)
1173#define	 ID_AA64MMFR1_HPDS_HPD		(UL(0x1) << ID_AA64MMFR1_HPDS_SHIFT)
1174#define	 ID_AA64MMFR1_HPDS_TTPBHA	(UL(0x2) << ID_AA64MMFR1_HPDS_SHIFT)
1175#define	ID_AA64MMFR1_LO_SHIFT		16
1176#define	ID_AA64MMFR1_LO_MASK		(UL(0xf) << ID_AA64MMFR1_LO_SHIFT)
1177#define	ID_AA64MMFR1_LO_VAL(x)		((x) & ID_AA64MMFR1_LO_MASK)
1178#define	 ID_AA64MMFR1_LO_NONE		(UL(0x0) << ID_AA64MMFR1_LO_SHIFT)
1179#define	 ID_AA64MMFR1_LO_IMPL		(UL(0x1) << ID_AA64MMFR1_LO_SHIFT)
1180#define	ID_AA64MMFR1_PAN_SHIFT		20
1181#define	ID_AA64MMFR1_PAN_MASK		(UL(0xf) << ID_AA64MMFR1_PAN_SHIFT)
1182#define	ID_AA64MMFR1_PAN_VAL(x)		((x) & ID_AA64MMFR1_PAN_MASK)
1183#define	 ID_AA64MMFR1_PAN_NONE		(UL(0x0) << ID_AA64MMFR1_PAN_SHIFT)
1184#define	 ID_AA64MMFR1_PAN_IMPL		(UL(0x1) << ID_AA64MMFR1_PAN_SHIFT)
1185#define	 ID_AA64MMFR1_PAN_ATS1E1	(UL(0x2) << ID_AA64MMFR1_PAN_SHIFT)
1186#define	 ID_AA64MMFR1_PAN_EPAN		(UL(0x2) << ID_AA64MMFR1_PAN_SHIFT)
1187#define	ID_AA64MMFR1_SpecSEI_SHIFT	24
1188#define	ID_AA64MMFR1_SpecSEI_MASK	(UL(0xf) << ID_AA64MMFR1_SpecSEI_SHIFT)
1189#define	ID_AA64MMFR1_SpecSEI_VAL(x)	((x) & ID_AA64MMFR1_SpecSEI_MASK)
1190#define	 ID_AA64MMFR1_SpecSEI_NONE	(UL(0x0) << ID_AA64MMFR1_SpecSEI_SHIFT)
1191#define	 ID_AA64MMFR1_SpecSEI_IMPL	(UL(0x1) << ID_AA64MMFR1_SpecSEI_SHIFT)
1192#define	ID_AA64MMFR1_XNX_SHIFT		28
1193#define	ID_AA64MMFR1_XNX_MASK		(UL(0xf) << ID_AA64MMFR1_XNX_SHIFT)
1194#define	ID_AA64MMFR1_XNX_VAL(x)		((x) & ID_AA64MMFR1_XNX_MASK)
1195#define	 ID_AA64MMFR1_XNX_NONE		(UL(0x0) << ID_AA64MMFR1_XNX_SHIFT)
1196#define	 ID_AA64MMFR1_XNX_IMPL		(UL(0x1) << ID_AA64MMFR1_XNX_SHIFT)
1197#define	ID_AA64MMFR1_TWED_SHIFT		32
1198#define	ID_AA64MMFR1_TWED_MASK		(UL(0xf) << ID_AA64MMFR1_TWED_SHIFT)
1199#define	ID_AA64MMFR1_TWED_VAL(x)	((x) & ID_AA64MMFR1_TWED_MASK)
1200#define	 ID_AA64MMFR1_TWED_NONE		(UL(0x0) << ID_AA64MMFR1_TWED_SHIFT)
1201#define	 ID_AA64MMFR1_TWED_IMPL		(UL(0x1) << ID_AA64MMFR1_TWED_SHIFT)
1202#define	ID_AA64MMFR1_ETS_SHIFT		36
1203#define	ID_AA64MMFR1_ETS_MASK		(UL(0xf) << ID_AA64MMFR1_ETS_SHIFT)
1204#define	ID_AA64MMFR1_ETS_VAL(x)		((x) & ID_AA64MMFR1_ETS_MASK)
1205#define	 ID_AA64MMFR1_ETS_NONE		(UL(0x0) << ID_AA64MMFR1_ETS_SHIFT)
1206#define	 ID_AA64MMFR1_ETS_IMPL		(UL(0x1) << ID_AA64MMFR1_ETS_SHIFT)
1207#define	ID_AA64MMFR1_HCX_SHIFT		40
1208#define	ID_AA64MMFR1_HCX_MASK		(UL(0xf) << ID_AA64MMFR1_HCX_SHIFT)
1209#define	ID_AA64MMFR1_HCX_VAL(x)		((x) & ID_AA64MMFR1_HCX_MASK)
1210#define	 ID_AA64MMFR1_HCX_NONE		(UL(0x0) << ID_AA64MMFR1_HCX_SHIFT)
1211#define	 ID_AA64MMFR1_HCX_IMPL		(UL(0x1) << ID_AA64MMFR1_HCX_SHIFT)
1212#define	ID_AA64MMFR1_AFP_SHIFT		44
1213#define	ID_AA64MMFR1_AFP_MASK		(UL(0xf) << ID_AA64MMFR1_AFP_SHIFT)
1214#define	ID_AA64MMFR1_AFP_VAL(x)		((x) & ID_AA64MMFR1_AFP_MASK)
1215#define	 ID_AA64MMFR1_AFP_NONE		(UL(0x0) << ID_AA64MMFR1_AFP_SHIFT)
1216#define	 ID_AA64MMFR1_AFP_IMPL		(UL(0x1) << ID_AA64MMFR1_AFP_SHIFT)
1217#define	ID_AA64MMFR1_nTLBPA_SHIFT	48
1218#define	ID_AA64MMFR1_nTLBPA_MASK	(UL(0xf) << ID_AA64MMFR1_nTLBPA_SHIFT)
1219#define	ID_AA64MMFR1_nTLBPA_VAL(x)	((x) & ID_AA64MMFR1_nTLBPA_MASK)
1220#define	 ID_AA64MMFR1_nTLBPA_NONE	(UL(0x0) << ID_AA64MMFR1_nTLBPA_SHIFT)
1221#define	 ID_AA64MMFR1_nTLBPA_IMPL	(UL(0x1) << ID_AA64MMFR1_nTLBPA_SHIFT)
1222#define	ID_AA64MMFR1_TIDCP1_SHIFT	52
1223#define	ID_AA64MMFR1_TIDCP1_MASK	(UL(0xf) << ID_AA64MMFR1_TIDCP1_SHIFT)
1224#define	ID_AA64MMFR1_TIDCP1_VAL(x)	((x) & ID_AA64MMFR1_TIDCP1_MASK)
1225#define	 ID_AA64MMFR1_TIDCP1_NONE	(UL(0x0) << ID_AA64MMFR1_TIDCP1_SHIFT)
1226#define	 ID_AA64MMFR1_TIDCP1_IMPL	(UL(0x1) << ID_AA64MMFR1_TIDCP1_SHIFT)
1227#define	ID_AA64MMFR1_CMOVW_SHIFT	56
1228#define	ID_AA64MMFR1_CMOVW_MASK		(UL(0xf) << ID_AA64MMFR1_CMOVW_SHIFT)
1229#define	ID_AA64MMFR1_CMOVW_VAL(x)	((x) & ID_AA64MMFR1_CMOVW_MASK)
1230#define	 ID_AA64MMFR1_CMOVW_NONE	(UL(0x0) << ID_AA64MMFR1_CMOVW_SHIFT)
1231#define	 ID_AA64MMFR1_CMOVW_IMPL	(UL(0x1) << ID_AA64MMFR1_CMOVW_SHIFT)
1232
1233/* ID_AA64MMFR2_EL1 */
1234#define	ID_AA64MMFR2_EL1		MRS_REG(ID_AA64MMFR2_EL1)
1235#define	ID_AA64MMFR2_EL1_REG		MRS_REG_ALT_NAME(ID_AA64MMFR2_EL1)
1236#define	ID_AA64MMFR2_EL1_op0		3
1237#define	ID_AA64MMFR2_EL1_op1		0
1238#define	ID_AA64MMFR2_EL1_CRn		0
1239#define	ID_AA64MMFR2_EL1_CRm		7
1240#define	ID_AA64MMFR2_EL1_op2		2
1241#define	ID_AA64MMFR2_CnP_SHIFT		0
1242#define	ID_AA64MMFR2_CnP_MASK		(UL(0xf) << ID_AA64MMFR2_CnP_SHIFT)
1243#define	ID_AA64MMFR2_CnP_VAL(x)		((x) & ID_AA64MMFR2_CnP_MASK)
1244#define	 ID_AA64MMFR2_CnP_NONE		(UL(0x0) << ID_AA64MMFR2_CnP_SHIFT)
1245#define	 ID_AA64MMFR2_CnP_IMPL		(UL(0x1) << ID_AA64MMFR2_CnP_SHIFT)
1246#define	ID_AA64MMFR2_UAO_SHIFT		4
1247#define	ID_AA64MMFR2_UAO_MASK		(UL(0xf) << ID_AA64MMFR2_UAO_SHIFT)
1248#define	ID_AA64MMFR2_UAO_VAL(x)		((x) & ID_AA64MMFR2_UAO_MASK)
1249#define	 ID_AA64MMFR2_UAO_NONE		(UL(0x0) << ID_AA64MMFR2_UAO_SHIFT)
1250#define	 ID_AA64MMFR2_UAO_IMPL		(UL(0x1) << ID_AA64MMFR2_UAO_SHIFT)
1251#define	ID_AA64MMFR2_LSM_SHIFT		8
1252#define	ID_AA64MMFR2_LSM_MASK		(UL(0xf) << ID_AA64MMFR2_LSM_SHIFT)
1253#define	ID_AA64MMFR2_LSM_VAL(x)		((x) & ID_AA64MMFR2_LSM_MASK)
1254#define	 ID_AA64MMFR2_LSM_NONE		(UL(0x0) << ID_AA64MMFR2_LSM_SHIFT)
1255#define	 ID_AA64MMFR2_LSM_IMPL		(UL(0x1) << ID_AA64MMFR2_LSM_SHIFT)
1256#define	ID_AA64MMFR2_IESB_SHIFT		12
1257#define	ID_AA64MMFR2_IESB_MASK		(UL(0xf) << ID_AA64MMFR2_IESB_SHIFT)
1258#define	ID_AA64MMFR2_IESB_VAL(x)	((x) & ID_AA64MMFR2_IESB_MASK)
1259#define	 ID_AA64MMFR2_IESB_NONE		(UL(0x0) << ID_AA64MMFR2_IESB_SHIFT)
1260#define	 ID_AA64MMFR2_IESB_IMPL		(UL(0x1) << ID_AA64MMFR2_IESB_SHIFT)
1261#define	ID_AA64MMFR2_VARange_SHIFT	16
1262#define	ID_AA64MMFR2_VARange_MASK	(UL(0xf) << ID_AA64MMFR2_VARange_SHIFT)
1263#define	ID_AA64MMFR2_VARange_VAL(x)	((x) & ID_AA64MMFR2_VARange_MASK)
1264#define	 ID_AA64MMFR2_VARange_48	(UL(0x0) << ID_AA64MMFR2_VARange_SHIFT)
1265#define	 ID_AA64MMFR2_VARange_52	(UL(0x1) << ID_AA64MMFR2_VARange_SHIFT)
1266#define	ID_AA64MMFR2_CCIDX_SHIFT	20
1267#define	ID_AA64MMFR2_CCIDX_MASK		(UL(0xf) << ID_AA64MMFR2_CCIDX_SHIFT)
1268#define	ID_AA64MMFR2_CCIDX_VAL(x)	((x) & ID_AA64MMFR2_CCIDX_MASK)
1269#define	 ID_AA64MMFR2_CCIDX_32		(UL(0x0) << ID_AA64MMFR2_CCIDX_SHIFT)
1270#define	 ID_AA64MMFR2_CCIDX_64		(UL(0x1) << ID_AA64MMFR2_CCIDX_SHIFT)
1271#define	ID_AA64MMFR2_NV_SHIFT		24
1272#define	ID_AA64MMFR2_NV_MASK		(UL(0xf) << ID_AA64MMFR2_NV_SHIFT)
1273#define	ID_AA64MMFR2_NV_VAL(x)		((x) & ID_AA64MMFR2_NV_MASK)
1274#define	 ID_AA64MMFR2_NV_NONE		(UL(0x0) << ID_AA64MMFR2_NV_SHIFT)
1275#define	 ID_AA64MMFR2_NV_8_3		(UL(0x1) << ID_AA64MMFR2_NV_SHIFT)
1276#define	 ID_AA64MMFR2_NV_8_4		(UL(0x2) << ID_AA64MMFR2_NV_SHIFT)
1277#define	ID_AA64MMFR2_ST_SHIFT		28
1278#define	ID_AA64MMFR2_ST_MASK		(UL(0xf) << ID_AA64MMFR2_ST_SHIFT)
1279#define	ID_AA64MMFR2_ST_VAL(x)		((x) & ID_AA64MMFR2_ST_MASK)
1280#define	 ID_AA64MMFR2_ST_NONE		(UL(0x0) << ID_AA64MMFR2_ST_SHIFT)
1281#define	 ID_AA64MMFR2_ST_IMPL		(UL(0x1) << ID_AA64MMFR2_ST_SHIFT)
1282#define	ID_AA64MMFR2_AT_SHIFT		32
1283#define	ID_AA64MMFR2_AT_MASK		(UL(0xf) << ID_AA64MMFR2_AT_SHIFT)
1284#define	ID_AA64MMFR2_AT_VAL(x)		((x) & ID_AA64MMFR2_AT_MASK)
1285#define	 ID_AA64MMFR2_AT_NONE		(UL(0x0) << ID_AA64MMFR2_AT_SHIFT)
1286#define	 ID_AA64MMFR2_AT_IMPL		(UL(0x1) << ID_AA64MMFR2_AT_SHIFT)
1287#define	ID_AA64MMFR2_IDS_SHIFT		36
1288#define	ID_AA64MMFR2_IDS_MASK		(UL(0xf) << ID_AA64MMFR2_IDS_SHIFT)
1289#define	ID_AA64MMFR2_IDS_VAL(x)		((x) & ID_AA64MMFR2_IDS_MASK)
1290#define	 ID_AA64MMFR2_IDS_NONE		(UL(0x0) << ID_AA64MMFR2_IDS_SHIFT)
1291#define	 ID_AA64MMFR2_IDS_IMPL		(UL(0x1) << ID_AA64MMFR2_IDS_SHIFT)
1292#define	ID_AA64MMFR2_FWB_SHIFT		40
1293#define	ID_AA64MMFR2_FWB_MASK		(UL(0xf) << ID_AA64MMFR2_FWB_SHIFT)
1294#define	ID_AA64MMFR2_FWB_VAL(x)		((x) & ID_AA64MMFR2_FWB_MASK)
1295#define	 ID_AA64MMFR2_FWB_NONE		(UL(0x0) << ID_AA64MMFR2_FWB_SHIFT)
1296#define	 ID_AA64MMFR2_FWB_IMPL		(UL(0x1) << ID_AA64MMFR2_FWB_SHIFT)
1297#define	ID_AA64MMFR2_TTL_SHIFT		48
1298#define	ID_AA64MMFR2_TTL_MASK		(UL(0xf) << ID_AA64MMFR2_TTL_SHIFT)
1299#define	ID_AA64MMFR2_TTL_VAL(x)		((x) & ID_AA64MMFR2_TTL_MASK)
1300#define	 ID_AA64MMFR2_TTL_NONE		(UL(0x0) << ID_AA64MMFR2_TTL_SHIFT)
1301#define	 ID_AA64MMFR2_TTL_IMPL		(UL(0x1) << ID_AA64MMFR2_TTL_SHIFT)
1302#define	ID_AA64MMFR2_BBM_SHIFT		52
1303#define	ID_AA64MMFR2_BBM_MASK		(UL(0xf) << ID_AA64MMFR2_BBM_SHIFT)
1304#define	ID_AA64MMFR2_BBM_VAL(x)		((x) & ID_AA64MMFR2_BBM_MASK)
1305#define	 ID_AA64MMFR2_BBM_LEVEL0	(UL(0x0) << ID_AA64MMFR2_BBM_SHIFT)
1306#define	 ID_AA64MMFR2_BBM_LEVEL1	(UL(0x1) << ID_AA64MMFR2_BBM_SHIFT)
1307#define	 ID_AA64MMFR2_BBM_LEVEL2	(UL(0x2) << ID_AA64MMFR2_BBM_SHIFT)
1308#define	ID_AA64MMFR2_EVT_SHIFT		56
1309#define	ID_AA64MMFR2_EVT_MASK		(UL(0xf) << ID_AA64MMFR2_EVT_SHIFT)
1310#define	ID_AA64MMFR2_EVT_VAL(x)		((x) & ID_AA64MMFR2_EVT_MASK)
1311#define	 ID_AA64MMFR2_EVT_NONE		(UL(0x0) << ID_AA64MMFR2_EVT_SHIFT)
1312#define	 ID_AA64MMFR2_EVT_8_2		(UL(0x1) << ID_AA64MMFR2_EVT_SHIFT)
1313#define	 ID_AA64MMFR2_EVT_8_5		(UL(0x2) << ID_AA64MMFR2_EVT_SHIFT)
1314#define	ID_AA64MMFR2_E0PD_SHIFT		60
1315#define	ID_AA64MMFR2_E0PD_MASK		(UL(0xf) << ID_AA64MMFR2_E0PD_SHIFT)
1316#define	ID_AA64MMFR2_E0PD_VAL(x)	((x) & ID_AA64MMFR2_E0PD_MASK)
1317#define	 ID_AA64MMFR2_E0PD_NONE		(UL(0x0) << ID_AA64MMFR2_E0PD_SHIFT)
1318#define	 ID_AA64MMFR2_E0PD_IMPL		(UL(0x1) << ID_AA64MMFR2_E0PD_SHIFT)
1319
1320/* ID_AA64MMFR3_EL1 */
1321#define	ID_AA64MMFR3_EL1		MRS_REG(ID_AA64MMFR3_EL1)
1322#define	ID_AA64MMFR3_EL1_REG		MRS_REG_ALT_NAME(ID_AA64MMFR3_EL1)
1323#define	ID_AA64MMFR3_EL1_op0		3
1324#define	ID_AA64MMFR3_EL1_op1		0
1325#define	ID_AA64MMFR3_EL1_CRn		0
1326#define	ID_AA64MMFR3_EL1_CRm		7
1327#define	ID_AA64MMFR3_EL1_op2		3
1328#define	ID_AA64MMFR3_TCRX_SHIFT		0
1329#define	ID_AA64MMFR3_TCRX_MASK		(UL(0xf) << ID_AA64MMFR3_TCRX_SHIFT)
1330#define	ID_AA64MMFR3_TCRX_VAL(x)	((x) & ID_AA64MMFR3_TCRX_MASK)
1331#define	 ID_AA64MMFR3_TCRX_NONE		(UL(0x0) << ID_AA64MMFR3_TCRX_SHIFT)
1332#define	 ID_AA64MMFR3_TCRX_IMPL		(UL(0x1) << ID_AA64MMFR3_TCRX_SHIFT)
1333#define	ID_AA64MMFR3_SCTLRX_SHIFT	4
1334#define	ID_AA64MMFR3_SCTLRX_MASK	(UL(0xf) << ID_AA64MMFR3_SCTLRX_SHIFT)
1335#define	ID_AA64MMFR3_SCTLRX_VAL(x)	((x) & ID_AA64MMFR3_SCTLRX_MASK)
1336#define	 ID_AA64MMFR3_SCTLRX_NONE	(UL(0x0) << ID_AA64MMFR3_SCTLRX_SHIFT)
1337#define	 ID_AA64MMFR3_SCTLRX_IMPL	(UL(0x1) << ID_AA64MMFR3_SCTLRX_SHIFT)
1338#define	ID_AA64MMFR3_MEC_SHIFT		28
1339#define	ID_AA64MMFR3_MEC_MASK		(UL(0xf) << ID_AA64MMFR3_MEC_SHIFT)
1340#define	ID_AA64MMFR3_MEC_VAL(x)	((x) & ID_AA64MMFR3_MEC_MASK)
1341#define	 ID_AA64MMFR3_MEC_NONE		(UL(0x0) << ID_AA64MMFR3_MEC_SHIFT)
1342#define	 ID_AA64MMFR3_MEC_IMPL		(UL(0x1) << ID_AA64MMFR3_MEC_SHIFT)
1343#define	ID_AA64MMFR3_Spec_FPACC_SHIFT	60
1344#define	ID_AA64MMFR3_Spec_FPACC_MASK	(UL(0xf) << ID_AA64MMFR3_Spec_FPACC_SHIFT)
1345#define	ID_AA64MMFR3_Spec_FPACC_VAL(x)	((x) & ID_AA64MMFR3_Spec_FPACC_MASK)
1346#define	 ID_AA64MMFR3_Spec_FPACC_NONE	(UL(0x0) << ID_AA64MMFR3_Spec_FPACC_SHIFT)
1347#define	 ID_AA64MMFR3_Spec_FPACC_IMPL	(UL(0x1) << ID_AA64MMFR3_Spec_FPACC_SHIFT)
1348
1349/* ID_AA64MMFR4_EL1 */
1350#define	ID_AA64MMFR4_EL1		MRS_REG(ID_AA64MMFR4_EL1)
1351#define	ID_AA64MMFR4_EL1_REG		MRS_REG_ALT_NAME(ID_AA64MMFR4_EL1)
1352#define	ID_AA64MMFR4_EL1_op0		3
1353#define	ID_AA64MMFR4_EL1_op1		0
1354#define	ID_AA64MMFR4_EL1_CRn		0
1355#define	ID_AA64MMFR4_EL1_CRm		7
1356#define	ID_AA64MMFR4_EL1_op2		4
1357
1358/* ID_AA64PFR0_EL1 */
1359#define	ID_AA64PFR0_EL1			MRS_REG(ID_AA64PFR0_EL1)
1360#define	ID_AA64PFR0_EL1_REG		MRS_REG_ALT_NAME(ID_AA64PFR0_EL1)
1361#define	ID_AA64PFR0_EL1_op0		3
1362#define	ID_AA64PFR0_EL1_op1		0
1363#define	ID_AA64PFR0_EL1_CRn		0
1364#define	ID_AA64PFR0_EL1_CRm		4
1365#define	ID_AA64PFR0_EL1_op2		0
1366#define	ID_AA64PFR0_EL0_SHIFT		0
1367#define	ID_AA64PFR0_EL0_MASK		(UL(0xf) << ID_AA64PFR0_EL0_SHIFT)
1368#define	ID_AA64PFR0_EL0_VAL(x)		((x) & ID_AA64PFR0_EL0_MASK)
1369#define	 ID_AA64PFR0_EL0_64		(UL(0x1) << ID_AA64PFR0_EL0_SHIFT)
1370#define	 ID_AA64PFR0_EL0_64_32		(UL(0x2) << ID_AA64PFR0_EL0_SHIFT)
1371#define	ID_AA64PFR0_EL1_SHIFT		4
1372#define	ID_AA64PFR0_EL1_MASK		(UL(0xf) << ID_AA64PFR0_EL1_SHIFT)
1373#define	ID_AA64PFR0_EL1_VAL(x)		((x) & ID_AA64PFR0_EL1_MASK)
1374#define	 ID_AA64PFR0_EL1_64		(UL(0x1) << ID_AA64PFR0_EL1_SHIFT)
1375#define	 ID_AA64PFR0_EL1_64_32		(UL(0x2) << ID_AA64PFR0_EL1_SHIFT)
1376#define	ID_AA64PFR0_EL2_SHIFT		8
1377#define	ID_AA64PFR0_EL2_MASK		(UL(0xf) << ID_AA64PFR0_EL2_SHIFT)
1378#define	ID_AA64PFR0_EL2_VAL(x)		((x) & ID_AA64PFR0_EL2_MASK)
1379#define	 ID_AA64PFR0_EL2_NONE		(UL(0x0) << ID_AA64PFR0_EL2_SHIFT)
1380#define	 ID_AA64PFR0_EL2_64		(UL(0x1) << ID_AA64PFR0_EL2_SHIFT)
1381#define	 ID_AA64PFR0_EL2_64_32		(UL(0x2) << ID_AA64PFR0_EL2_SHIFT)
1382#define	ID_AA64PFR0_EL3_SHIFT		12
1383#define	ID_AA64PFR0_EL3_MASK		(UL(0xf) << ID_AA64PFR0_EL3_SHIFT)
1384#define	ID_AA64PFR0_EL3_VAL(x)		((x) & ID_AA64PFR0_EL3_MASK)
1385#define	 ID_AA64PFR0_EL3_NONE		(UL(0x0) << ID_AA64PFR0_EL3_SHIFT)
1386#define	 ID_AA64PFR0_EL3_64		(UL(0x1) << ID_AA64PFR0_EL3_SHIFT)
1387#define	 ID_AA64PFR0_EL3_64_32		(UL(0x2) << ID_AA64PFR0_EL3_SHIFT)
1388#define	ID_AA64PFR0_FP_SHIFT		16
1389#define	ID_AA64PFR0_FP_MASK		(UL(0xf) << ID_AA64PFR0_FP_SHIFT)
1390#define	ID_AA64PFR0_FP_VAL(x)		((x) & ID_AA64PFR0_FP_MASK)
1391#define	 ID_AA64PFR0_FP_IMPL		(UL(0x0) << ID_AA64PFR0_FP_SHIFT)
1392#define	 ID_AA64PFR0_FP_HP		(UL(0x1) << ID_AA64PFR0_FP_SHIFT)
1393#define	 ID_AA64PFR0_FP_NONE		(UL(0xf) << ID_AA64PFR0_FP_SHIFT)
1394#define	ID_AA64PFR0_AdvSIMD_SHIFT	20
1395#define	ID_AA64PFR0_AdvSIMD_MASK	(UL(0xf) << ID_AA64PFR0_AdvSIMD_SHIFT)
1396#define	ID_AA64PFR0_AdvSIMD_VAL(x)	((x) & ID_AA64PFR0_AdvSIMD_MASK)
1397#define	 ID_AA64PFR0_AdvSIMD_IMPL	(UL(0x0) << ID_AA64PFR0_AdvSIMD_SHIFT)
1398#define	 ID_AA64PFR0_AdvSIMD_HP		(UL(0x1) << ID_AA64PFR0_AdvSIMD_SHIFT)
1399#define	 ID_AA64PFR0_AdvSIMD_NONE	(UL(0xf) << ID_AA64PFR0_AdvSIMD_SHIFT)
1400#define	ID_AA64PFR0_GIC_BITS		0x4 /* Number of bits in GIC field */
1401#define	ID_AA64PFR0_GIC_SHIFT		24
1402#define	ID_AA64PFR0_GIC_MASK		(UL(0xf) << ID_AA64PFR0_GIC_SHIFT)
1403#define	ID_AA64PFR0_GIC_VAL(x)		((x) & ID_AA64PFR0_GIC_MASK)
1404#define	 ID_AA64PFR0_GIC_CPUIF_NONE	(UL(0x0) << ID_AA64PFR0_GIC_SHIFT)
1405#define	 ID_AA64PFR0_GIC_CPUIF_EN	(UL(0x1) << ID_AA64PFR0_GIC_SHIFT)
1406#define	 ID_AA64PFR0_GIC_CPUIF_4_1	(UL(0x3) << ID_AA64PFR0_GIC_SHIFT)
1407#define	ID_AA64PFR0_RAS_SHIFT		28
1408#define	ID_AA64PFR0_RAS_MASK		(UL(0xf) << ID_AA64PFR0_RAS_SHIFT)
1409#define	ID_AA64PFR0_RAS_VAL(x)		((x) & ID_AA64PFR0_RAS_MASK)
1410#define	 ID_AA64PFR0_RAS_NONE		(UL(0x0) << ID_AA64PFR0_RAS_SHIFT)
1411#define	 ID_AA64PFR0_RAS_IMPL		(UL(0x1) << ID_AA64PFR0_RAS_SHIFT)
1412#define	 ID_AA64PFR0_RAS_8_4		(UL(0x2) << ID_AA64PFR0_RAS_SHIFT)
1413#define	ID_AA64PFR0_SVE_SHIFT		32
1414#define	ID_AA64PFR0_SVE_MASK		(UL(0xf) << ID_AA64PFR0_SVE_SHIFT)
1415#define	ID_AA64PFR0_SVE_VAL(x)		((x) & ID_AA64PFR0_SVE_MASK)
1416#define	 ID_AA64PFR0_SVE_NONE		(UL(0x0) << ID_AA64PFR0_SVE_SHIFT)
1417#define	 ID_AA64PFR0_SVE_IMPL		(UL(0x1) << ID_AA64PFR0_SVE_SHIFT)
1418#define	ID_AA64PFR0_SEL2_SHIFT		36
1419#define	ID_AA64PFR0_SEL2_MASK		(UL(0xf) << ID_AA64PFR0_SEL2_SHIFT)
1420#define	ID_AA64PFR0_SEL2_VAL(x)		((x) & ID_AA64PFR0_SEL2_MASK)
1421#define	 ID_AA64PFR0_SEL2_NONE		(UL(0x0) << ID_AA64PFR0_SEL2_SHIFT)
1422#define	 ID_AA64PFR0_SEL2_IMPL		(UL(0x1) << ID_AA64PFR0_SEL2_SHIFT)
1423#define	ID_AA64PFR0_MPAM_SHIFT		40
1424#define	ID_AA64PFR0_MPAM_MASK		(UL(0xf) << ID_AA64PFR0_MPAM_SHIFT)
1425#define	ID_AA64PFR0_MPAM_VAL(x)		((x) & ID_AA64PFR0_MPAM_MASK)
1426#define	 ID_AA64PFR0_MPAM_NONE		(UL(0x0) << ID_AA64PFR0_MPAM_SHIFT)
1427#define	 ID_AA64PFR0_MPAM_IMPL		(UL(0x1) << ID_AA64PFR0_MPAM_SHIFT)
1428#define	ID_AA64PFR0_AMU_SHIFT		44
1429#define	ID_AA64PFR0_AMU_MASK		(UL(0xf) << ID_AA64PFR0_AMU_SHIFT)
1430#define	ID_AA64PFR0_AMU_VAL(x)		((x) & ID_AA64PFR0_AMU_MASK)
1431#define	 ID_AA64PFR0_AMU_NONE		(UL(0x0) << ID_AA64PFR0_AMU_SHIFT)
1432#define	 ID_AA64PFR0_AMU_V1		(UL(0x1) << ID_AA64PFR0_AMU_SHIFT)
1433#define	 ID_AA64PFR0_AMU_V1_1		(UL(0x2) << ID_AA64PFR0_AMU_SHIFT)
1434#define	ID_AA64PFR0_DIT_SHIFT		48
1435#define	ID_AA64PFR0_DIT_MASK		(UL(0xf) << ID_AA64PFR0_DIT_SHIFT)
1436#define	ID_AA64PFR0_DIT_VAL(x)		((x) & ID_AA64PFR0_DIT_MASK)
1437#define	 ID_AA64PFR0_DIT_NONE		(UL(0x0) << ID_AA64PFR0_DIT_SHIFT)
1438#define	 ID_AA64PFR0_DIT_PSTATE		(UL(0x1) << ID_AA64PFR0_DIT_SHIFT)
1439#define	ID_AA64PFR0_RME_SHIFT		52
1440#define	ID_AA64PFR0_RME_MASK		(UL(0xf) << ID_AA64PFR0_RME_SHIFT)
1441#define	ID_AA64PFR0_RME_VAL(x)		((x) & ID_AA64PFR0_RME_MASK)
1442#define	 ID_AA64PFR0_RME_NONE		(UL(0x0) << ID_AA64PFR0_RME_SHIFT)
1443#define	 ID_AA64PFR0_RME_IMPL		(UL(0x1) << ID_AA64PFR0_RME_SHIFT)
1444#define	ID_AA64PFR0_CSV2_SHIFT		56
1445#define	ID_AA64PFR0_CSV2_MASK		(UL(0xf) << ID_AA64PFR0_CSV2_SHIFT)
1446#define	ID_AA64PFR0_CSV2_VAL(x)		((x) & ID_AA64PFR0_CSV2_MASK)
1447#define	 ID_AA64PFR0_CSV2_NONE		(UL(0x0) << ID_AA64PFR0_CSV2_SHIFT)
1448#define	 ID_AA64PFR0_CSV2_ISOLATED	(UL(0x1) << ID_AA64PFR0_CSV2_SHIFT)
1449#define	 ID_AA64PFR0_CSV2_SCXTNUM	(UL(0x2) << ID_AA64PFR0_CSV2_SHIFT)
1450#define	 ID_AA64PFR0_CSV2_3		(UL(0x3) << ID_AA64PFR0_CSV2_SHIFT)
1451#define	ID_AA64PFR0_CSV3_SHIFT		60
1452#define	ID_AA64PFR0_CSV3_MASK		(UL(0xf) << ID_AA64PFR0_CSV3_SHIFT)
1453#define	ID_AA64PFR0_CSV3_VAL(x)		((x) & ID_AA64PFR0_CSV3_MASK)
1454#define	 ID_AA64PFR0_CSV3_NONE		(UL(0x0) << ID_AA64PFR0_CSV3_SHIFT)
1455#define	 ID_AA64PFR0_CSV3_ISOLATED	(UL(0x1) << ID_AA64PFR0_CSV3_SHIFT)
1456
1457/* ID_AA64PFR1_EL1 */
1458#define	ID_AA64PFR1_EL1			MRS_REG(ID_AA64PFR1_EL1)
1459#define	ID_AA64PFR1_EL1_REG		MRS_REG_ALT_NAME(ID_AA64PFR1_EL1)
1460#define	ID_AA64PFR1_EL1_op0		3
1461#define	ID_AA64PFR1_EL1_op1		0
1462#define	ID_AA64PFR1_EL1_CRn		0
1463#define	ID_AA64PFR1_EL1_CRm		4
1464#define	ID_AA64PFR1_EL1_op2		1
1465#define	ID_AA64PFR1_BT_SHIFT		0
1466#define	ID_AA64PFR1_BT_MASK		(UL(0xf) << ID_AA64PFR1_BT_SHIFT)
1467#define	ID_AA64PFR1_BT_VAL(x)		((x) & ID_AA64PFR1_BT_MASK)
1468#define	 ID_AA64PFR1_BT_NONE		(UL(0x0) << ID_AA64PFR1_BT_SHIFT)
1469#define	 ID_AA64PFR1_BT_IMPL		(UL(0x1) << ID_AA64PFR1_BT_SHIFT)
1470#define	ID_AA64PFR1_SSBS_SHIFT		4
1471#define	ID_AA64PFR1_SSBS_MASK		(UL(0xf) << ID_AA64PFR1_SSBS_SHIFT)
1472#define	ID_AA64PFR1_SSBS_VAL(x)		((x) & ID_AA64PFR1_SSBS_MASK)
1473#define	 ID_AA64PFR1_SSBS_NONE		(UL(0x0) << ID_AA64PFR1_SSBS_SHIFT)
1474#define	 ID_AA64PFR1_SSBS_PSTATE	(UL(0x1) << ID_AA64PFR1_SSBS_SHIFT)
1475#define	 ID_AA64PFR1_SSBS_PSTATE_MSR	(UL(0x2) << ID_AA64PFR1_SSBS_SHIFT)
1476#define	ID_AA64PFR1_MTE_SHIFT		8
1477#define	ID_AA64PFR1_MTE_MASK		(UL(0xf) << ID_AA64PFR1_MTE_SHIFT)
1478#define	ID_AA64PFR1_MTE_VAL(x)		((x) & ID_AA64PFR1_MTE_MASK)
1479#define	 ID_AA64PFR1_MTE_NONE		(UL(0x0) << ID_AA64PFR1_MTE_SHIFT)
1480#define	 ID_AA64PFR1_MTE_MTE		(UL(0x1) << ID_AA64PFR1_MTE_SHIFT)
1481#define	 ID_AA64PFR1_MTE_MTE2		(UL(0x2) << ID_AA64PFR1_MTE_SHIFT)
1482#define	 ID_AA64PFR1_MTE_MTE3		(UL(0x3) << ID_AA64PFR1_MTE_SHIFT)
1483#define	ID_AA64PFR1_RAS_frac_SHIFT	12
1484#define	ID_AA64PFR1_RAS_frac_MASK	(UL(0xf) << ID_AA64PFR1_RAS_frac_SHIFT)
1485#define	ID_AA64PFR1_RAS_frac_VAL(x)	((x) & ID_AA64PFR1_RAS_frac_MASK)
1486#define	 ID_AA64PFR1_RAS_frac_p0	(UL(0x0) << ID_AA64PFR1_RAS_frac_SHIFT)
1487#define	 ID_AA64PFR1_RAS_frac_p1	(UL(0x1) << ID_AA64PFR1_RAS_frac_SHIFT)
1488#define	ID_AA64PFR1_MPAM_frac_SHIFT	16
1489#define	ID_AA64PFR1_MPAM_frac_MASK	(UL(0xf) << ID_AA64PFR1_MPAM_frac_SHIFT)
1490#define	ID_AA64PFR1_MPAM_frac_VAL(x)	((x) & ID_AA64PFR1_MPAM_frac_MASK)
1491#define	 ID_AA64PFR1_MPAM_frac_p0	(UL(0x0) << ID_AA64PFR1_MPAM_frac_SHIFT)
1492#define	 ID_AA64PFR1_MPAM_frac_p1	(UL(0x1) << ID_AA64PFR1_MPAM_frac_SHIFT)
1493#define	ID_AA64PFR1_SME_SHIFT		24
1494#define	ID_AA64PFR1_SME_MASK		(UL(0xf) << ID_AA64PFR1_SME_SHIFT)
1495#define	ID_AA64PFR1_SME_VAL(x)		((x) & ID_AA64PFR1_SME_MASK)
1496#define	 ID_AA64PFR1_SME_NONE		(UL(0x0) << ID_AA64PFR1_SME_SHIFT)
1497#define	 ID_AA64PFR1_SME_SME		(UL(0x1) << ID_AA64PFR1_SME_SHIFT)
1498#define	 ID_AA64PFR1_SME_SME2		(UL(0x2) << ID_AA64PFR1_SME_SHIFT)
1499#define	ID_AA64PFR1_RNDR_trap_SHIFT	28
1500#define	ID_AA64PFR1_RNDR_trap_MASK	(UL(0xf) << ID_AA64PFR1_RNDR_trap_SHIFT)
1501#define	ID_AA64PFR1_RNDR_trap_VAL(x)	((x) & ID_AA64PFR1_RNDR_trap_MASK)
1502#define	 ID_AA64PFR1_RNDR_trap_NONE	(UL(0x0) << ID_AA64PFR1_RNDR_trap_SHIFT)
1503#define	 ID_AA64PFR1_RNDR_trap_IMPL	(UL(0x1) << ID_AA64PFR1_RNDR_trap_SHIFT)
1504#define	ID_AA64PFR1_CSV2_frac_SHIFT	32
1505#define	ID_AA64PFR1_CSV2_frac_MASK	(UL(0xf) << ID_AA64PFR1_CSV2_frac_SHIFT)
1506#define	ID_AA64PFR1_CSV2_frac_VAL(x)	((x) & ID_AA64PFR1_CSV2_frac_MASK)
1507#define	 ID_AA64PFR1_CSV2_frac_p0	(UL(0x0) << ID_AA64PFR1_CSV2_frac_SHIFT)
1508#define	 ID_AA64PFR1_CSV2_frac_p1	(UL(0x1) << ID_AA64PFR1_CSV2_frac_SHIFT)
1509#define	 ID_AA64PFR1_CSV2_frac_p2	(UL(0x2) << ID_AA64PFR1_CSV2_frac_SHIFT)
1510#define	ID_AA64PFR1_NMI_SHIFT		36
1511#define	ID_AA64PFR1_NMI_MASK		(UL(0xf) << ID_AA64PFR1_NMI_SHIFT)
1512#define	ID_AA64PFR1_NMI_VAL(x)		((x) & ID_AA64PFR1_NMI_MASK)
1513#define	 ID_AA64PFR1_NMI_NONE		(UL(0x0) << ID_AA64PFR1_NMI_SHIFT)
1514#define	 ID_AA64PFR1_NMI_IMPL		(UL(0x1) << ID_AA64PFR1_NMI_SHIFT)
1515
1516/* ID_AA64PFR2_EL1 */
1517#define	ID_AA64PFR2_EL1			MRS_REG(ID_AA64PFR2_EL1)
1518#define	ID_AA64PFR2_EL1_REG		MRS_REG_ALT_NAME(ID_AA64PFR2_EL1)
1519#define	ID_AA64PFR2_EL1_op0		3
1520#define	ID_AA64PFR2_EL1_op1		0
1521#define	ID_AA64PFR2_EL1_CRn		0
1522#define	ID_AA64PFR2_EL1_CRm		4
1523#define	ID_AA64PFR2_EL1_op2		2
1524
1525/* ID_AA64ZFR0_EL1 */
1526#define	ID_AA64ZFR0_EL1			MRS_REG(ID_AA64ZFR0_EL1)
1527#define	ID_AA64ZFR0_EL1_REG		MRS_REG_ALT_NAME(ID_AA64ZFR0_EL1)
1528#define	ID_AA64ZFR0_EL1_op0		3
1529#define	ID_AA64ZFR0_EL1_op1		0
1530#define	ID_AA64ZFR0_EL1_CRn		0
1531#define	ID_AA64ZFR0_EL1_CRm		4
1532#define	ID_AA64ZFR0_EL1_op2		4
1533#define	ID_AA64ZFR0_SVEver_SHIFT	0
1534#define	ID_AA64ZFR0_SVEver_MASK		(UL(0xf) << ID_AA64ZFR0_SVEver_SHIFT)
1535#define	ID_AA64ZFR0_SVEver_VAL(x)	((x) & ID_AA64ZFR0_SVEver_MASK
1536#define	ID_AA64ZFR0_SVEver_SVE1		(UL(0x0) << ID_AA64ZFR0_SVEver_SHIFT)
1537#define	ID_AA64ZFR0_SVEver_SVE2		(UL(0x1) << ID_AA64ZFR0_SVEver_SHIFT)
1538#define	ID_AA64ZFR0_SVEver_SVE2P1	(UL(0x2) << ID_AA64ZFR0_SVEver_SHIFT)
1539#define	ID_AA64ZFR0_AES_SHIFT		4
1540#define	ID_AA64ZFR0_AES_MASK		(UL(0xf) << ID_AA64ZFR0_AES_SHIFT)
1541#define	ID_AA64ZFR0_AES_VAL(x)		((x) & ID_AA64ZFR0_AES_MASK
1542#define	ID_AA64ZFR0_AES_NONE		(UL(0x0) << ID_AA64ZFR0_AES_SHIFT)
1543#define	ID_AA64ZFR0_AES_BASE		(UL(0x1) << ID_AA64ZFR0_AES_SHIFT)
1544#define	ID_AA64ZFR0_AES_PMULL		(UL(0x2) << ID_AA64ZFR0_AES_SHIFT)
1545#define	ID_AA64ZFR0_BitPerm_SHIFT	16
1546#define	ID_AA64ZFR0_BitPerm_MASK	(UL(0xf) << ID_AA64ZFR0_BitPerm_SHIFT)
1547#define	ID_AA64ZFR0_BitPerm_VAL(x)	((x) & ID_AA64ZFR0_BitPerm_MASK
1548#define	ID_AA64ZFR0_BitPerm_NONE	(UL(0x0) << ID_AA64ZFR0_BitPerm_SHIFT)
1549#define	ID_AA64ZFR0_BitPerm_IMPL	(UL(0x1) << ID_AA64ZFR0_BitPerm_SHIFT)
1550#define	ID_AA64ZFR0_BF16_SHIFT		20
1551#define	ID_AA64ZFR0_BF16_MASK		(UL(0xf) << ID_AA64ZFR0_BF16_SHIFT)
1552#define	ID_AA64ZFR0_BF16_VAL(x)		((x) & ID_AA64ZFR0_BF16_MASK
1553#define	ID_AA64ZFR0_BF16_NONE		(UL(0x0) << ID_AA64ZFR0_BF16_SHIFT)
1554#define	ID_AA64ZFR0_BF16_BASE		(UL(0x1) << ID_AA64ZFR0_BF16_SHIFT)
1555#define	ID_AA64ZFR0_BF16_EBF		(UL(0x1) << ID_AA64ZFR0_BF16_SHIFT)
1556#define	ID_AA64ZFR0_SHA3_SHIFT		32
1557#define	ID_AA64ZFR0_SHA3_MASK		(UL(0xf) << ID_AA64ZFR0_SHA3_SHIFT)
1558#define	ID_AA64ZFR0_SHA3_VAL(x)		((x) & ID_AA64ZFR0_SHA3_MASK
1559#define	ID_AA64ZFR0_SHA3_NONE		(UL(0x0) << ID_AA64ZFR0_SHA3_SHIFT)
1560#define	ID_AA64ZFR0_SHA3_IMPL		(UL(0x1) << ID_AA64ZFR0_SHA3_SHIFT)
1561#define	ID_AA64ZFR0_SM4_SHIFT		40
1562#define	ID_AA64ZFR0_SM4_MASK		(UL(0xf) << ID_AA64ZFR0_SM4_SHIFT)
1563#define	ID_AA64ZFR0_SM4_VAL(x)		((x) & ID_AA64ZFR0_SM4_MASK
1564#define	ID_AA64ZFR0_SM4_NONE		(UL(0x0) << ID_AA64ZFR0_SM4_SHIFT)
1565#define	ID_AA64ZFR0_SM4_IMPL		(UL(0x1) << ID_AA64ZFR0_SM4_SHIFT)
1566#define	ID_AA64ZFR0_I8MM_SHIFT		44
1567#define	ID_AA64ZFR0_I8MM_MASK		(UL(0xf) << ID_AA64ZFR0_I8MM_SHIFT)
1568#define	ID_AA64ZFR0_I8MM_VAL(x)		((x) & ID_AA64ZFR0_I8MM_MASK
1569#define	ID_AA64ZFR0_I8MM_NONE		(UL(0x0) << ID_AA64ZFR0_I8MM_SHIFT)
1570#define	ID_AA64ZFR0_I8MM_IMPL		(UL(0x1) << ID_AA64ZFR0_I8MM_SHIFT)
1571#define	ID_AA64ZFR0_F32MM_SHIFT		52
1572#define	ID_AA64ZFR0_F32MM_MASK		(UL(0xf) << ID_AA64ZFR0_F32MM_SHIFT)
1573#define	ID_AA64ZFR0_F32MM_VAL(x)	((x) & ID_AA64ZFR0_F32MM_MASK
1574#define	ID_AA64ZFR0_F32MM_NONE		(UL(0x0) << ID_AA64ZFR0_F32MM_SHIFT)
1575#define	ID_AA64ZFR0_F32MM_IMPL		(UL(0x1) << ID_AA64ZFR0_F32MM_SHIFT)
1576#define	ID_AA64ZFR0_F64MM_SHIFT		56
1577#define	ID_AA64ZFR0_F64MM_MASK		(UL(0xf) << ID_AA64ZFR0_F64MM_SHIFT)
1578#define	ID_AA64ZFR0_F64MM_VAL(x)	((x) & ID_AA64ZFR0_F64MM_MASK
1579#define	ID_AA64ZFR0_F64MM_NONE		(UL(0x0) << ID_AA64ZFR0_F64MM_SHIFT)
1580#define	ID_AA64ZFR0_F64MM_IMPL		(UL(0x1) << ID_AA64ZFR0_F64MM_SHIFT)
1581
1582/* ID_ISAR5_EL1 */
1583#define	ID_ISAR5_EL1			MRS_REG(ID_ISAR5_EL1)
1584#define	ID_ISAR5_EL1_op0		0x3
1585#define	ID_ISAR5_EL1_op1		0x0
1586#define	ID_ISAR5_EL1_CRn		0x0
1587#define	ID_ISAR5_EL1_CRm		0x2
1588#define	ID_ISAR5_EL1_op2		0x5
1589#define	ID_ISAR5_SEVL_SHIFT		0
1590#define	ID_ISAR5_SEVL_MASK		(UL(0xf) << ID_ISAR5_SEVL_SHIFT)
1591#define	ID_ISAR5_SEVL_VAL(x)		((x) & ID_ISAR5_SEVL_MASK)
1592#define	 ID_ISAR5_SEVL_NOP		(UL(0x0) << ID_ISAR5_SEVL_SHIFT)
1593#define	 ID_ISAR5_SEVL_IMPL		(UL(0x1) << ID_ISAR5_SEVL_SHIFT)
1594#define	ID_ISAR5_AES_SHIFT		4
1595#define	ID_ISAR5_AES_MASK		(UL(0xf) << ID_ISAR5_AES_SHIFT)
1596#define	ID_ISAR5_AES_VAL(x)		((x) & ID_ISAR5_AES_MASK)
1597#define	 ID_ISAR5_AES_NONE		(UL(0x0) << ID_ISAR5_AES_SHIFT)
1598#define	 ID_ISAR5_AES_BASE		(UL(0x1) << ID_ISAR5_AES_SHIFT)
1599#define	 ID_ISAR5_AES_VMULL		(UL(0x2) << ID_ISAR5_AES_SHIFT)
1600#define	ID_ISAR5_SHA1_SHIFT		8
1601#define	ID_ISAR5_SHA1_MASK		(UL(0xf) << ID_ISAR5_SHA1_SHIFT)
1602#define	ID_ISAR5_SHA1_VAL(x)		((x) & ID_ISAR5_SHA1_MASK)
1603#define	 ID_ISAR5_SHA1_NONE		(UL(0x0) << ID_ISAR5_SHA1_SHIFT)
1604#define	 ID_ISAR5_SHA1_IMPL		(UL(0x1) << ID_ISAR5_SHA1_SHIFT)
1605#define	ID_ISAR5_SHA2_SHIFT		12
1606#define	ID_ISAR5_SHA2_MASK		(UL(0xf) << ID_ISAR5_SHA2_SHIFT)
1607#define	ID_ISAR5_SHA2_VAL(x)		((x) & ID_ISAR5_SHA2_MASK)
1608#define	 ID_ISAR5_SHA2_NONE		(UL(0x0) << ID_ISAR5_SHA2_SHIFT)
1609#define	 ID_ISAR5_SHA2_IMPL		(UL(0x1) << ID_ISAR5_SHA2_SHIFT)
1610#define	ID_ISAR5_CRC32_SHIFT		16
1611#define	ID_ISAR5_CRC32_MASK		(UL(0xf) << ID_ISAR5_CRC32_SHIFT)
1612#define	ID_ISAR5_CRC32_VAL(x)		((x) & ID_ISAR5_CRC32_MASK)
1613#define	 ID_ISAR5_CRC32_NONE		(UL(0x0) << ID_ISAR5_CRC32_SHIFT)
1614#define	 ID_ISAR5_CRC32_IMPL		(UL(0x1) << ID_ISAR5_CRC32_SHIFT)
1615#define	ID_ISAR5_RDM_SHIFT		24
1616#define	ID_ISAR5_RDM_MASK		(UL(0xf) << ID_ISAR5_RDM_SHIFT)
1617#define	ID_ISAR5_RDM_VAL(x)		((x) & ID_ISAR5_RDM_MASK)
1618#define	 ID_ISAR5_RDM_NONE		(UL(0x0) << ID_ISAR5_RDM_SHIFT)
1619#define	 ID_ISAR5_RDM_IMPL		(UL(0x1) << ID_ISAR5_RDM_SHIFT)
1620#define	ID_ISAR5_VCMA_SHIFT		28
1621#define	ID_ISAR5_VCMA_MASK		(UL(0xf) << ID_ISAR5_VCMA_SHIFT)
1622#define	ID_ISAR5_VCMA_VAL(x)		((x) & ID_ISAR5_VCMA_MASK)
1623#define	 ID_ISAR5_VCMA_NONE		(UL(0x0) << ID_ISAR5_VCMA_SHIFT)
1624#define	 ID_ISAR5_VCMA_IMPL		(UL(0x1) << ID_ISAR5_VCMA_SHIFT)
1625
1626/* MAIR_EL1 - Memory Attribute Indirection Register */
1627#define	MAIR_EL1_REG			MRS_REG_ALT_NAME(MAIR_EL1)
1628#define	MAIR_EL1_op0			3
1629#define	MAIR_EL1_op1			0
1630#define	MAIR_EL1_CRn			10
1631#define	MAIR_EL1_CRm			2
1632#define	MAIR_EL1_op2			0
1633#define	MAIR_ATTR_MASK(idx)		(UL(0xff) << ((n)* 8))
1634#define	MAIR_ATTR(attr, idx)		((attr) << ((idx) * 8))
1635#define	 MAIR_DEVICE_nGnRnE		UL(0x00)
1636#define	 MAIR_DEVICE_nGnRE		UL(0x04)
1637#define	 MAIR_NORMAL_NC			UL(0x44)
1638#define	 MAIR_NORMAL_WT			UL(0xbb)
1639#define	 MAIR_NORMAL_WB			UL(0xff)
1640
1641/* MAIR_EL12 */
1642#define	MAIR_EL12_REG			MRS_REG_ALT_NAME(MAIR_EL12)
1643#define	MAIR_EL12_op0			3
1644#define	MAIR_EL12_op1			5
1645#define	MAIR_EL12_CRn			10
1646#define	MAIR_EL12_CRm			2
1647#define	MAIR_EL12_op2			0
1648
1649/* MDCCINT_EL1 */
1650#define	MDCCINT_EL1			MRS_REG(MDCCINT_EL1)
1651#define	MDCCINT_EL1_op0			2
1652#define	MDCCINT_EL1_op1			0
1653#define	MDCCINT_EL1_CRn			0
1654#define	MDCCINT_EL1_CRm			2
1655#define	MDCCINT_EL1_op2			0
1656
1657/* MDCCSR_EL0 */
1658#define	MDCCSR_EL0			MRS_REG(MDCCSR_EL0)
1659#define	MDCCSR_EL0_op0			2
1660#define	MDCCSR_EL0_op1			3
1661#define	MDCCSR_EL0_CRn			0
1662#define	MDCCSR_EL0_CRm			1
1663#define	MDCCSR_EL0_op2			0
1664
1665/* MDSCR_EL1 - Monitor Debug System Control Register */
1666#define	MDSCR_EL1			MRS_REG(MDSCR_EL1)
1667#define	MDSCR_EL1_op0			2
1668#define	MDSCR_EL1_op1			0
1669#define	MDSCR_EL1_CRn			0
1670#define	MDSCR_EL1_CRm			2
1671#define	MDSCR_EL1_op2			2
1672#define	MDSCR_SS_SHIFT			0
1673#define	MDSCR_SS			(UL(0x1) << MDSCR_SS_SHIFT)
1674#define	MDSCR_KDE_SHIFT			13
1675#define	MDSCR_KDE			(UL(0x1) << MDSCR_KDE_SHIFT)
1676#define	MDSCR_MDE_SHIFT			15
1677#define	MDSCR_MDE			(UL(0x1) << MDSCR_MDE_SHIFT)
1678
1679/* MIDR_EL1 - Main ID Register */
1680#define	MIDR_EL1			MRS_REG(MIDR_EL1)
1681#define	MIDR_EL1_op0			3
1682#define	MIDR_EL1_op1			0
1683#define	MIDR_EL1_CRn			0
1684#define	MIDR_EL1_CRm			0
1685#define	MIDR_EL1_op2			0
1686
1687/* MPIDR_EL1 - Multiprocessor Affinity Register */
1688#define	MPIDR_EL1			MRS_REG(MPIDR_EL1)
1689#define	MPIDR_EL1_op0			3
1690#define	MPIDR_EL1_op1			0
1691#define	MPIDR_EL1_CRn			0
1692#define	MPIDR_EL1_CRm			0
1693#define	MPIDR_EL1_op2			5
1694#define	MPIDR_AFF0_SHIFT		0
1695#define	MPIDR_AFF0_MASK			(UL(0xff) << MPIDR_AFF0_SHIFT)
1696#define	MPIDR_AFF0_VAL(x)		((x) & MPIDR_AFF0_MASK)
1697#define	MPIDR_AFF1_SHIFT		8
1698#define	MPIDR_AFF1_MASK			(UL(0xff) << MPIDR_AFF1_SHIFT)
1699#define	MPIDR_AFF1_VAL(x)		((x) & MPIDR_AFF1_MASK)
1700#define	MPIDR_AFF2_SHIFT		16
1701#define	MPIDR_AFF2_MASK			(UL(0xff) << MPIDR_AFF2_SHIFT)
1702#define	MPIDR_AFF2_VAL(x)		((x) & MPIDR_AFF2_MASK)
1703#define	MPIDR_MT_SHIFT			24
1704#define	MPIDR_MT_MASK			(UL(0x1) << MPIDR_MT_SHIFT)
1705#define	MPIDR_U_SHIFT			30
1706#define	MPIDR_U_MASK			(UL(0x1) << MPIDR_U_SHIFT)
1707#define	MPIDR_AFF3_SHIFT		32
1708#define	MPIDR_AFF3_MASK			(UL(0xff) << MPIDR_AFF3_SHIFT)
1709#define	MPIDR_AFF3_VAL(x)		((x) & MPIDR_AFF3_MASK)
1710
1711/* MVFR0_EL1 */
1712#define	MVFR0_EL1			MRS_REG(MVFR0_EL1)
1713#define	MVFR0_EL1_op0			0x3
1714#define	MVFR0_EL1_op1			0x0
1715#define	MVFR0_EL1_CRn			0x0
1716#define	MVFR0_EL1_CRm			0x3
1717#define	MVFR0_EL1_op2			0x0
1718#define	MVFR0_SIMDReg_SHIFT		0
1719#define	MVFR0_SIMDReg_MASK		(UL(0xf) << MVFR0_SIMDReg_SHIFT)
1720#define	MVFR0_SIMDReg_VAL(x)		((x) & MVFR0_SIMDReg_MASK)
1721#define	 MVFR0_SIMDReg_NONE		(UL(0x0) << MVFR0_SIMDReg_SHIFT)
1722#define	 MVFR0_SIMDReg_FP		(UL(0x1) << MVFR0_SIMDReg_SHIFT)
1723#define	 MVFR0_SIMDReg_AdvSIMD		(UL(0x2) << MVFR0_SIMDReg_SHIFT)
1724#define	MVFR0_FPSP_SHIFT		4
1725#define	MVFR0_FPSP_MASK			(UL(0xf) << MVFR0_FPSP_SHIFT)
1726#define	MVFR0_FPSP_VAL(x)		((x) & MVFR0_FPSP_MASK)
1727#define	 MVFR0_FPSP_NONE		(UL(0x0) << MVFR0_FPSP_SHIFT)
1728#define	 MVFR0_FPSP_VFP_v2		(UL(0x1) << MVFR0_FPSP_SHIFT)
1729#define	 MVFR0_FPSP_VFP_v3_v4		(UL(0x2) << MVFR0_FPSP_SHIFT)
1730#define	MVFR0_FPDP_SHIFT		8
1731#define	MVFR0_FPDP_MASK			(UL(0xf) << MVFR0_FPDP_SHIFT)
1732#define	MVFR0_FPDP_VAL(x)		((x) & MVFR0_FPDP_MASK)
1733#define	 MVFR0_FPDP_NONE		(UL(0x0) << MVFR0_FPDP_SHIFT)
1734#define	 MVFR0_FPDP_VFP_v2		(UL(0x1) << MVFR0_FPDP_SHIFT)
1735#define	 MVFR0_FPDP_VFP_v3_v4		(UL(0x2) << MVFR0_FPDP_SHIFT)
1736#define	MVFR0_FPTrap_SHIFT		12
1737#define	MVFR0_FPTrap_MASK		(UL(0xf) << MVFR0_FPTrap_SHIFT)
1738#define	MVFR0_FPTrap_VAL(x)		((x) & MVFR0_FPTrap_MASK)
1739#define	 MVFR0_FPTrap_NONE		(UL(0x0) << MVFR0_FPTrap_SHIFT)
1740#define	 MVFR0_FPTrap_IMPL		(UL(0x1) << MVFR0_FPTrap_SHIFT)
1741#define	MVFR0_FPDivide_SHIFT		16
1742#define	MVFR0_FPDivide_MASK		(UL(0xf) << MVFR0_FPDivide_SHIFT)
1743#define	MVFR0_FPDivide_VAL(x)		((x) & MVFR0_FPDivide_MASK)
1744#define	 MVFR0_FPDivide_NONE		(UL(0x0) << MVFR0_FPDivide_SHIFT)
1745#define	 MVFR0_FPDivide_IMPL		(UL(0x1) << MVFR0_FPDivide_SHIFT)
1746#define	MVFR0_FPSqrt_SHIFT		20
1747#define	MVFR0_FPSqrt_MASK		(UL(0xf) << MVFR0_FPSqrt_SHIFT)
1748#define	MVFR0_FPSqrt_VAL(x)		((x) & MVFR0_FPSqrt_MASK)
1749#define	 MVFR0_FPSqrt_NONE		(UL(0x0) << MVFR0_FPSqrt_SHIFT)
1750#define	 MVFR0_FPSqrt_IMPL		(UL(0x1) << MVFR0_FPSqrt_SHIFT)
1751#define	MVFR0_FPShVec_SHIFT		24
1752#define	MVFR0_FPShVec_MASK		(UL(0xf) << MVFR0_FPShVec_SHIFT)
1753#define	MVFR0_FPShVec_VAL(x)		((x) & MVFR0_FPShVec_MASK)
1754#define	 MVFR0_FPShVec_NONE		(UL(0x0) << MVFR0_FPShVec_SHIFT)
1755#define	 MVFR0_FPShVec_IMPL		(UL(0x1) << MVFR0_FPShVec_SHIFT)
1756#define	MVFR0_FPRound_SHIFT		28
1757#define	MVFR0_FPRound_MASK		(UL(0xf) << MVFR0_FPRound_SHIFT)
1758#define	MVFR0_FPRound_VAL(x)		((x) & MVFR0_FPRound_MASK)
1759#define	 MVFR0_FPRound_NONE		(UL(0x0) << MVFR0_FPRound_SHIFT)
1760#define	 MVFR0_FPRound_IMPL		(UL(0x1) << MVFR0_FPRound_SHIFT)
1761
1762/* MVFR1_EL1 */
1763#define	MVFR1_EL1			MRS_REG(MVFR1_EL1)
1764#define	MVFR1_EL1_op0			0x3
1765#define	MVFR1_EL1_op1			0x0
1766#define	MVFR1_EL1_CRn			0x0
1767#define	MVFR1_EL1_CRm			0x3
1768#define	MVFR1_EL1_op2			0x1
1769#define	MVFR1_FPFtZ_SHIFT		0
1770#define	MVFR1_FPFtZ_MASK		(UL(0xf) << MVFR1_FPFtZ_SHIFT)
1771#define	MVFR1_FPFtZ_VAL(x)		((x) & MVFR1_FPFtZ_MASK)
1772#define	 MVFR1_FPFtZ_NONE		(UL(0x0) << MVFR1_FPFtZ_SHIFT)
1773#define	 MVFR1_FPFtZ_IMPL		(UL(0x1) << MVFR1_FPFtZ_SHIFT)
1774#define	MVFR1_FPDNaN_SHIFT		4
1775#define	MVFR1_FPDNaN_MASK		(UL(0xf) << MVFR1_FPDNaN_SHIFT)
1776#define	MVFR1_FPDNaN_VAL(x)		((x) & MVFR1_FPDNaN_MASK)
1777#define	 MVFR1_FPDNaN_NONE		(UL(0x0) << MVFR1_FPDNaN_SHIFT)
1778#define	 MVFR1_FPDNaN_IMPL		(UL(0x1) << MVFR1_FPDNaN_SHIFT)
1779#define	MVFR1_SIMDLS_SHIFT		8
1780#define	MVFR1_SIMDLS_MASK		(UL(0xf) << MVFR1_SIMDLS_SHIFT)
1781#define	MVFR1_SIMDLS_VAL(x)		((x) & MVFR1_SIMDLS_MASK)
1782#define	 MVFR1_SIMDLS_NONE		(UL(0x0) << MVFR1_SIMDLS_SHIFT)
1783#define	 MVFR1_SIMDLS_IMPL		(UL(0x1) << MVFR1_SIMDLS_SHIFT)
1784#define	MVFR1_SIMDInt_SHIFT		12
1785#define	MVFR1_SIMDInt_MASK		(UL(0xf) << MVFR1_SIMDInt_SHIFT)
1786#define	MVFR1_SIMDInt_VAL(x)		((x) & MVFR1_SIMDInt_MASK)
1787#define	 MVFR1_SIMDInt_NONE		(UL(0x0) << MVFR1_SIMDInt_SHIFT)
1788#define	 MVFR1_SIMDInt_IMPL		(UL(0x1) << MVFR1_SIMDInt_SHIFT)
1789#define	MVFR1_SIMDSP_SHIFT		16
1790#define	MVFR1_SIMDSP_MASK		(UL(0xf) << MVFR1_SIMDSP_SHIFT)
1791#define	MVFR1_SIMDSP_VAL(x)		((x) & MVFR1_SIMDSP_MASK)
1792#define	 MVFR1_SIMDSP_NONE		(UL(0x0) << MVFR1_SIMDSP_SHIFT)
1793#define	 MVFR1_SIMDSP_IMPL		(UL(0x1) << MVFR1_SIMDSP_SHIFT)
1794#define	MVFR1_SIMDHP_SHIFT		20
1795#define	MVFR1_SIMDHP_MASK		(UL(0xf) << MVFR1_SIMDHP_SHIFT)
1796#define	MVFR1_SIMDHP_VAL(x)		((x) & MVFR1_SIMDHP_MASK)
1797#define	 MVFR1_SIMDHP_NONE		(UL(0x0) << MVFR1_SIMDHP_SHIFT)
1798#define	 MVFR1_SIMDHP_CONV_SP		(UL(0x1) << MVFR1_SIMDHP_SHIFT)
1799#define	 MVFR1_SIMDHP_ARITH		(UL(0x2) << MVFR1_SIMDHP_SHIFT)
1800#define	MVFR1_FPHP_SHIFT		24
1801#define	MVFR1_FPHP_MASK			(UL(0xf) << MVFR1_FPHP_SHIFT)
1802#define	MVFR1_FPHP_VAL(x)		((x) & MVFR1_FPHP_MASK)
1803#define	 MVFR1_FPHP_NONE		(UL(0x0) << MVFR1_FPHP_SHIFT)
1804#define	 MVFR1_FPHP_CONV_SP		(UL(0x1) << MVFR1_FPHP_SHIFT)
1805#define	 MVFR1_FPHP_CONV_DP		(UL(0x2) << MVFR1_FPHP_SHIFT)
1806#define	 MVFR1_FPHP_ARITH		(UL(0x3) << MVFR1_FPHP_SHIFT)
1807#define	MVFR1_SIMDFMAC_SHIFT		28
1808#define	MVFR1_SIMDFMAC_MASK		(UL(0xf) << MVFR1_SIMDFMAC_SHIFT)
1809#define	MVFR1_SIMDFMAC_VAL(x)		((x) & MVFR1_SIMDFMAC_MASK)
1810#define	 MVFR1_SIMDFMAC_NONE		(UL(0x0) << MVFR1_SIMDFMAC_SHIFT)
1811#define	 MVFR1_SIMDFMAC_IMPL		(UL(0x1) << MVFR1_SIMDFMAC_SHIFT)
1812
1813/* OSDLR_EL1 */
1814#define	OSDLR_EL1			MRS_REG(OSDLR_EL1)
1815#define	OSDLR_EL1_op0			2
1816#define	OSDLR_EL1_op1			0
1817#define	OSDLR_EL1_CRn			1
1818#define	OSDLR_EL1_CRm			3
1819#define	OSDLR_EL1_op2			4
1820
1821/* OSLAR_EL1 */
1822#define	OSLAR_EL1			MRS_REG(OSLAR_EL1)
1823#define	OSLAR_EL1_op0			2
1824#define	OSLAR_EL1_op1			0
1825#define	OSLAR_EL1_CRn			1
1826#define	OSLAR_EL1_CRm			0
1827#define	OSLAR_EL1_op2			4
1828
1829/* OSLSR_EL1 */
1830#define	OSLSR_EL1			MRS_REG(OSLSR_EL1)
1831#define	OSLSR_EL1_op0			2
1832#define	OSLSR_EL1_op1			0
1833#define	OSLSR_EL1_CRn			1
1834#define	OSLSR_EL1_CRm			1
1835#define	OSLSR_EL1_op2			4
1836
1837/* PAR_EL1 - Physical Address Register */
1838#define	PAR_F_SHIFT		0
1839#define	PAR_F			(0x1 << PAR_F_SHIFT)
1840#define	PAR_SUCCESS(x)		(((x) & PAR_F) == 0)
1841/* When PAR_F == 0 (success) */
1842#define	PAR_LOW_MASK		0xfff
1843#define	PAR_SH_SHIFT		7
1844#define	PAR_SH_MASK		(0x3 << PAR_SH_SHIFT)
1845#define	PAR_NS_SHIFT		9
1846#define	PAR_NS_MASK		(0x3 << PAR_NS_SHIFT)
1847#define	PAR_PA_SHIFT		12
1848#define	PAR_PA_MASK		0x0000fffffffff000
1849#define	PAR_ATTR_SHIFT		56
1850#define	PAR_ATTR_MASK		(0xff << PAR_ATTR_SHIFT)
1851/* When PAR_F == 1 (aborted) */
1852#define	PAR_FST_SHIFT		1
1853#define	PAR_FST_MASK		(0x3f << PAR_FST_SHIFT)
1854#define	PAR_PTW_SHIFT		8
1855#define	PAR_PTW_MASK		(0x1 << PAR_PTW_SHIFT)
1856#define	PAR_S_SHIFT		9
1857#define	PAR_S_MASK		(0x1 << PAR_S_SHIFT)
1858
1859/* PMBIDR_EL1 */
1860#define	PMBIDR_EL1			MRS_REG(PMBIDR_EL1)
1861#define	PMBIDR_EL1_REG			MRS_REG_ALT_NAME(PMBIDR_EL1)
1862#define	PMBIDR_EL1_op0			3
1863#define	PMBIDR_EL1_op1			0
1864#define	PMBIDR_EL1_CRn			9
1865#define	PMBIDR_EL1_CRm			10
1866#define	PMBIDR_EL1_op2			7
1867#define	PMBIDR_Align_SHIFT		0
1868#define	PMBIDR_Align_MASK		(UL(0xf) << PMBIDR_Align_SHIFT)
1869#define	PMBIDR_P_SHIFT			4
1870#define	PMBIDR_P			(UL(0x1) << PMBIDR_P_SHIFT)
1871#define	PMBIDR_F_SHIFT			5
1872#define	PMBIDR_F			(UL(0x1) << PMBIDR_F_SHIFT)
1873
1874/* PMBLIMITR_EL1 */
1875#define	PMBLIMITR_EL1			MRS_REG(PMBLIMITR_EL1)
1876#define	PMBLIMITR_EL1_REG		MRS_REG_ALT_NAME(PMBLIMITR_EL1)
1877#define	PMBLIMITR_EL1_op0		3
1878#define	PMBLIMITR_EL1_op1		0
1879#define	PMBLIMITR_EL1_CRn		9
1880#define	PMBLIMITR_EL1_CRm		10
1881#define	PMBLIMITR_EL1_op2		0
1882#define	PMBLIMITR_E_SHIFT		0
1883#define	PMBLIMITR_E			(UL(0x1) << PMBLIMITR_E_SHIFT)
1884#define	PMBLIMITR_FM_SHIFT		1
1885#define	PMBLIMITR_FM_MASK		(UL(0x3) << PMBLIMITR_FM_SHIFT)
1886#define	PMBLIMITR_PMFZ_SHIFT		5
1887#define	PMBLIMITR_PMFZ			(UL(0x1) << PMBLIMITR_PMFZ_SHIFT)
1888#define	PMBLIMITR_LIMIT_SHIFT		12
1889#define	PMBLIMITR_LIMIT_MASK		\
1890    (UL(0xfffffffffffff) << PMBLIMITR_LIMIT_SHIFT)
1891
1892/* PMBPTR_EL1 */
1893#define	PMBPTR_EL1			MRS_REG(PMBPTR_EL1)
1894#define	PMBPTR_EL1_REG			MRS_REG_ALT_NAME(PMBPTR_EL1)
1895#define	PMBPTR_EL1_op0			3
1896#define	PMBPTR_EL1_op1			0
1897#define	PMBPTR_EL1_CRn			9
1898#define	PMBPTR_EL1_CRm			10
1899#define	PMBPTR_EL1_op2			1
1900#define	PMBPTR_PTR_SHIFT		0
1901#define	PMBPTR_PTR_MASK			\
1902    (UL(0xffffffffffffffff) << PMBPTR_PTR_SHIFT)
1903
1904/* PMBSR_EL1 */
1905#define	PMBSR_EL1			MRS_REG(PMBSR_EL1)
1906#define	PMBSR_EL1_REG			MRS_REG_ALT_NAME(PMBSR_EL1)
1907#define	PMBSR_EL1_op0			3
1908#define	PMBSR_EL1_op1			0
1909#define	PMBSR_EL1_CRn			9
1910#define	PMBSR_EL1_CRm			10
1911#define	PMBSR_EL1_op2			3
1912#define	PMBSR_MSS_SHIFT			0
1913#define	PMBSR_MSS_MASK			(UL(0xffff) << PMBSR_MSS_SHIFT)
1914#define	PMBSR_MSS_BSC_MASK		(UL(0x3f) << PMBSR_MSS_SHIFT)
1915#define	PMBSR_MSS_FSC_MASK		(UL(0x3f) << PMBSR_MSS_SHIFT)
1916#define	PMBSR_COLL_SHIFT		16
1917#define	PMBSR_COLL			(UL(0x1) << PMBSR_COLL_SHIFT)
1918#define	PMBSR_S_SHIFT			17
1919#define	PMBSR_S				(UL(0x1) << PMBSR_S_SHIFT)
1920#define	PMBSR_EA_SHIFT			18
1921#define	PMBSR_EA			(UL(0x1) << PMBSR_EA_SHIFT)
1922#define	PMBSR_DL_SHIFT			19
1923#define	PMBSR_DL			(UL(0x1) << PMBSR_DL_SHIFT)
1924#define	PMBSR_EC_SHIFT			26
1925#define	PMBSR_EC_MASK			(UL(0x3f) << PMBSR_EC_SHIFT)
1926
1927/* PMCCFILTR_EL0 */
1928#define	PMCCFILTR_EL0			MRS_REG(PMCCFILTR_EL0)
1929#define	PMCCFILTR_EL0_op0		3
1930#define	PMCCFILTR_EL0_op1		3
1931#define	PMCCFILTR_EL0_CRn		14
1932#define	PMCCFILTR_EL0_CRm		15
1933#define	PMCCFILTR_EL0_op2		7
1934
1935/* PMCCNTR_EL0 */
1936#define	PMCCNTR_EL0			MRS_REG(PMCCNTR_EL0)
1937#define	PMCCNTR_EL0_op0			3
1938#define	PMCCNTR_EL0_op1			3
1939#define	PMCCNTR_EL0_CRn			9
1940#define	PMCCNTR_EL0_CRm			13
1941#define	PMCCNTR_EL0_op2			0
1942
1943/* PMCEID0_EL0 */
1944#define	PMCEID0_EL0			MRS_REG(PMCEID0_EL0)
1945#define	PMCEID0_EL0_op0			3
1946#define	PMCEID0_EL0_op1			3
1947#define	PMCEID0_EL0_CRn			9
1948#define	PMCEID0_EL0_CRm			12
1949#define	PMCEID0_EL0_op2			6
1950
1951/* PMCEID1_EL0 */
1952#define	PMCEID1_EL0			MRS_REG(PMCEID1_EL0)
1953#define	PMCEID1_EL0_op0			3
1954#define	PMCEID1_EL0_op1			3
1955#define	PMCEID1_EL0_CRn			9
1956#define	PMCEID1_EL0_CRm			12
1957#define	PMCEID1_EL0_op2			7
1958
1959/* PMCNTENCLR_EL0 */
1960#define	PMCNTENCLR_EL0			MRS_REG(PMCNTENCLR_EL0)
1961#define	PMCNTENCLR_EL0_op0		3
1962#define	PMCNTENCLR_EL0_op1		3
1963#define	PMCNTENCLR_EL0_CRn		9
1964#define	PMCNTENCLR_EL0_CRm		12
1965#define	PMCNTENCLR_EL0_op2		2
1966
1967/* PMCNTENSET_EL0 */
1968#define	PMCNTENSET_EL0			MRS_REG(PMCNTENSET_EL0)
1969#define	PMCNTENSET_EL0_op0		3
1970#define	PMCNTENSET_EL0_op1		3
1971#define	PMCNTENSET_EL0_CRn		9
1972#define	PMCNTENSET_EL0_CRm		12
1973#define	PMCNTENSET_EL0_op2		1
1974
1975/* PMCR_EL0 - Perfomance Monitoring Counters */
1976#define	PMCR_EL0			MRS_REG(PMCR_EL0)
1977#define	PMCR_EL0_op0			3
1978#define	PMCR_EL0_op1			3
1979#define	PMCR_EL0_CRn			9
1980#define	PMCR_EL0_CRm			12
1981#define	PMCR_EL0_op2			0
1982#define	PMCR_E				(1 << 0) /* Enable all counters */
1983#define	PMCR_P				(1 << 1) /* Reset all counters */
1984#define	PMCR_C				(1 << 2) /* Clock counter reset */
1985#define	PMCR_D				(1 << 3) /* CNTR counts every 64 clk cycles */
1986#define	PMCR_X				(1 << 4) /* Export to ext. monitoring (ETM) */
1987#define	PMCR_DP				(1 << 5) /* Disable CCNT if non-invasive debug*/
1988#define	PMCR_LC				(1 << 6) /* Long cycle count enable */
1989#define	PMCR_IMP_SHIFT			24	/* Implementer code */
1990#define	PMCR_IMP_MASK			(0xff << PMCR_IMP_SHIFT)
1991#define	 PMCR_IMP_ARM			0x41
1992#define	PMCR_IDCODE_SHIFT		16	/* Identification code */
1993#define	PMCR_IDCODE_MASK		(0xff << PMCR_IDCODE_SHIFT)
1994#define	 PMCR_IDCODE_CORTEX_A57		0x01
1995#define	 PMCR_IDCODE_CORTEX_A72		0x02
1996#define	 PMCR_IDCODE_CORTEX_A53		0x03
1997#define	 PMCR_IDCODE_CORTEX_A73		0x04
1998#define	 PMCR_IDCODE_CORTEX_A35		0x0a
1999#define	 PMCR_IDCODE_CORTEX_A76		0x0b
2000#define	 PMCR_IDCODE_NEOVERSE_N1	0x0c
2001#define	 PMCR_IDCODE_CORTEX_A77		0x10
2002#define	 PMCR_IDCODE_CORTEX_A55		0x45
2003#define	 PMCR_IDCODE_NEOVERSE_E1	0x46
2004#define	 PMCR_IDCODE_CORTEX_A75		0x4a
2005#define	PMCR_N_SHIFT			11  /* Number of counters implemented */
2006#define	PMCR_N_MASK			(0x1f << PMCR_N_SHIFT)
2007
2008/* PMEVCNTR<n>_EL0 */
2009#define	PMEVCNTR_EL0_op0		3
2010#define	PMEVCNTR_EL0_op1		3
2011#define	PMEVCNTR_EL0_CRn		14
2012#define	PMEVCNTR_EL0_CRm		8
2013/*
2014 * PMEVCNTRn_EL0_CRm[1:0] holds the upper 2 bits of 'n'
2015 * PMEVCNTRn_EL0_op2 holds the lower 3 bits of 'n'
2016 */
2017
2018/* PMEVTYPER<n>_EL0 - Performance Monitoring Event Type */
2019#define	PMEVTYPER_EL0_op0		3
2020#define	PMEVTYPER_EL0_op1		3
2021#define	PMEVTYPER_EL0_CRn		14
2022#define	PMEVTYPER_EL0_CRm		12
2023/*
2024 * PMEVTYPERn_EL0_CRm[1:0] holds the upper 2 bits of 'n'
2025 * PMEVTYPERn_EL0_op2 holds the lower 3 bits of 'n'
2026 */
2027#define	PMEVTYPER_EVTCOUNT_MASK		0x000003ff /* ARMv8.0 */
2028#define	PMEVTYPER_EVTCOUNT_8_1_MASK	0x0000ffff /* ARMv8.1+ */
2029#define	PMEVTYPER_MT			(1 << 25) /* Multithreading */
2030#define	PMEVTYPER_M			(1 << 26) /* Secure EL3 filtering */
2031#define	PMEVTYPER_NSH			(1 << 27) /* Non-secure hypervisor filtering */
2032#define	PMEVTYPER_NSU			(1 << 28) /* Non-secure user filtering */
2033#define	PMEVTYPER_NSK			(1 << 29) /* Non-secure kernel filtering */
2034#define	PMEVTYPER_U			(1 << 30) /* User filtering */
2035#define	PMEVTYPER_P			(1 << 31) /* Privileged filtering */
2036
2037/* PMINTENCLR_EL1 */
2038#define	PMINTENCLR_EL1			MRS_REG(PMINTENCLR_EL1)
2039#define	PMINTENCLR_EL1_op0		3
2040#define	PMINTENCLR_EL1_op1		0
2041#define	PMINTENCLR_EL1_CRn		9
2042#define	PMINTENCLR_EL1_CRm		14
2043#define	PMINTENCLR_EL1_op2		2
2044
2045/* PMINTENSET_EL1 */
2046#define	PMINTENSET_EL1			MRS_REG(PMINTENSET_EL1)
2047#define	PMINTENSET_EL1_op0		3
2048#define	PMINTENSET_EL1_op1		0
2049#define	PMINTENSET_EL1_CRn		9
2050#define	PMINTENSET_EL1_CRm		14
2051#define	PMINTENSET_EL1_op2		1
2052
2053/* PMMIR_EL1 */
2054#define	PMMIR_EL1			MRS_REG(PMMIR_EL1)
2055#define	PMMIR_EL1_op0			3
2056#define	PMMIR_EL1_op1			0
2057#define	PMMIR_EL1_CRn			9
2058#define	PMMIR_EL1_CRm			14
2059#define	PMMIR_EL1_op2			6
2060
2061/* PMOVSCLR_EL0 */
2062#define	PMOVSCLR_EL0			MRS_REG(PMOVSCLR_EL0)
2063#define	PMOVSCLR_EL0_op0		3
2064#define	PMOVSCLR_EL0_op1		3
2065#define	PMOVSCLR_EL0_CRn		9
2066#define	PMOVSCLR_EL0_CRm		12
2067#define	PMOVSCLR_EL0_op2		3
2068
2069/* PMOVSSET_EL0 */
2070#define	PMOVSSET_EL0			MRS_REG(PMOVSSET_EL0)
2071#define	PMOVSSET_EL0_op0		3
2072#define	PMOVSSET_EL0_op1		3
2073#define	PMOVSSET_EL0_CRn		9
2074#define	PMOVSSET_EL0_CRm		14
2075#define	PMOVSSET_EL0_op2		3
2076
2077/* PMSCR_EL1 */
2078#define	PMSCR_EL1			MRS_REG(PMSCR_EL1)
2079#define	PMSCR_EL1_REG			MRS_REG_ALT_NAME(PMSCR_EL1)
2080#define	PMSCR_EL1_op0			3
2081#define	PMSCR_EL1_op1			0
2082#define	PMSCR_EL1_CRn			9
2083#define	PMSCR_EL1_CRm			9
2084#define	PMSCR_EL1_op2			0
2085#define	PMSCR_E0SPE_SHIFT		0
2086#define	PMSCR_E0SPE			(UL(0x1) << PMSCR_E0SPE_SHIFT)
2087#define	PMSCR_E1SPE_SHIFT		1
2088#define	PMSCR_E1SPE			(UL(0x1) << PMSCR_E1SPE_SHIFT)
2089#define	PMSCR_CX_SHIFT			3
2090#define	PMSCR_CX			(UL(0x1) << PMSCR_CX_SHIFT)
2091#define	PMSCR_PA_SHIFT			4
2092#define	PMSCR_PA			(UL(0x1) << PMSCR_PA_SHIFT)
2093#define	PMSCR_TS_SHIFT			5
2094#define	PMSCR_TS			(UL(0x1) << PMSCR_TS_SHIFT)
2095#define	PMSCR_PCT_SHIFT			6
2096#define	PMSCR_PCT_MASK			(UL(0x3) << PMSCR_PCT_SHIFT)
2097
2098/* PMSELR_EL0 */
2099#define	PMSELR_EL0			MRS_REG(PMSELR_EL0)
2100#define	PMSELR_EL0_op0			3
2101#define	PMSELR_EL0_op1			3
2102#define	PMSELR_EL0_CRn			9
2103#define	PMSELR_EL0_CRm			12
2104#define	PMSELR_EL0_op2			5
2105#define	PMSELR_SEL_MASK			0x1f
2106
2107/* PMSEVFR_EL1 */
2108#define	PMSEVFR_EL1			MRS_REG(PMSEVFR_EL1)
2109#define	PMSEVFR_EL1_REG			MRS_REG_ALT_NAME(PMSEVFR_EL1)
2110#define	PMSEVFR_EL1_op0			3
2111#define	PMSEVFR_EL1_op1			0
2112#define	PMSEVFR_EL1_CRn			9
2113#define	PMSEVFR_EL1_CRm			9
2114#define	PMSEVFR_EL1_op2			5
2115
2116/* PMSFCR_EL1 */
2117#define	PMSFCR_EL1			MRS_REG(PMSFCR_EL1)
2118#define	PMSFCR_EL1_REG			MRS_REG_ALT_NAME(PMSFCR_EL1)
2119#define	PMSFCR_EL1_op0			3
2120#define	PMSFCR_EL1_op1			0
2121#define	PMSFCR_EL1_CRn			9
2122#define	PMSFCR_EL1_CRm			9
2123#define	PMSFCR_EL1_op2			4
2124#define	PMSFCR_FE_SHIFT			0
2125#define	PMSFCR_FE			(UL(0x1) << PMSFCR_FE_SHIFT)
2126#define	PMSFCR_FT_SHIFT			1
2127#define	PMSFCR_FT			(UL(0x1) << PMSFCR_FT_SHIFT)
2128#define	PMSFCR_FL_SHIFT			2
2129#define	PMSFCR_FL			(UL(0x1) << PMSFCR_FL_SHIFT)
2130#define	PMSFCR_FnE_SHIFT		3
2131#define	PMSFCR_FnE			(UL(0x1) << PMSFCR_FnE_SHIFT)
2132#define	PMSFCR_B_SHIFT			16
2133#define	PMSFCR_B			(UL(0x1) << PMSFCR_B_SHIFT)
2134#define	PMSFCR_LD_SHIFT			17
2135#define	PMSFCR_LD			(UL(0x1) << PMSFCR_LD_SHIFT)
2136#define	PMSFCR_ST_SHIFT			18
2137#define	PMSFCR_ST			(UL(0x1) << PMSFCR_ST_SHIFT)
2138
2139/* PMSICR_EL1 */
2140#define	PMSICR_EL1			MRS_REG(PMSICR_EL1)
2141#define	PMSICR_EL1_REG			MRS_REG_ALT_NAME(PMSICR_EL1)
2142#define	PMSICR_EL1_op0			3
2143#define	PMSICR_EL1_op1			0
2144#define	PMSICR_EL1_CRn			9
2145#define	PMSICR_EL1_CRm			9
2146#define	PMSICR_EL1_op2			2
2147#define	PMSICR_COUNT_SHIFT		0
2148#define	PMSICR_COUNT_MASK		(UL(0xffffffff) << PMSICR_COUNT_SHIFT)
2149#define	PMSICR_ECOUNT_SHIFT		56
2150#define	PMSICR_ECOUNT_MASK		(UL(0xff) << PMSICR_ECOUNT_SHIFT)
2151
2152/* PMSIDR_EL1 */
2153#define	PMSIDR_EL1			MRS_REG(PMSIDR_EL1)
2154#define	PMSIDR_EL1_REG			MRS_REG_ALT_NAME(PMSIDR_EL1)
2155#define	PMSIDR_EL1_op0			3
2156#define	PMSIDR_EL1_op1			0
2157#define	PMSIDR_EL1_CRn			9
2158#define	PMSIDR_EL1_CRm			9
2159#define	PMSIDR_EL1_op2			7
2160#define	PMSIDR_FE_SHIFT			0
2161#define	PMSIDR_FE			(UL(0x1) << PMSIDR_FE_SHIFT)
2162#define	PMSIDR_FT_SHIFT			1
2163#define	PMSIDR_FT			(UL(0x1) << PMSIDR_FT_SHIFT)
2164#define	PMSIDR_FL_SHIFT			2
2165#define	PMSIDR_FL			(UL(0x1) << PMSIDR_FL_SHIFT)
2166#define	PMSIDR_ArchInst_SHIFT		3
2167#define	PMSIDR_ArchInst			(UL(0x1) << PMSIDR_ArchInst_SHIFT)
2168#define	PMSIDR_LDS_SHIFT		4
2169#define	PMSIDR_LDS			(UL(0x1) << PMSIDR_LDS_SHIFT)
2170#define	PMSIDR_ERnd_SHIFT		5
2171#define	PMSIDR_ERnd			(UL(0x1) << PMSIDR_ERnd_SHIFT)
2172#define	PMSIDR_FnE_SHIFT		6
2173#define	PMSIDR_FnE			(UL(0x1) << PMSIDR_FnE_SHIFT)
2174#define	PMSIDR_Interval_SHIFT		8
2175#define	PMSIDR_Interval_MASK		(UL(0xf) << PMSIDR_Interval_SHIFT)
2176#define	PMSIDR_MaxSize_SHIFT		12
2177#define	PMSIDR_MaxSize_MASK		(UL(0xf) << PMSIDR_MaxSize_SHIFT)
2178#define	PMSIDR_CountSize_SHIFT		16
2179#define	PMSIDR_CountSize_MASK		(UL(0xf) << PMSIDR_CountSize_SHIFT)
2180#define	PMSIDR_Format_SHIFT		20
2181#define	PMSIDR_Format_MASK		(UL(0xf) << PMSIDR_Format_SHIFT)
2182#define	PMSIDR_PBT_SHIFT		24
2183#define	PMSIDR_PBT			(UL(0x1) << PMSIDR_PBT_SHIFT)
2184
2185/* PMSIRR_EL1 */
2186#define	PMSIRR_EL1			MRS_REG(PMSIRR_EL1)
2187#define	PMSIRR_EL1_REG			MRS_REG_ALT_NAME(PMSIRR_EL1)
2188#define	PMSIRR_EL1_op0			3
2189#define	PMSIRR_EL1_op1			0
2190#define	PMSIRR_EL1_CRn			9
2191#define	PMSIRR_EL1_CRm			9
2192#define	PMSIRR_EL1_op2			3
2193#define	PMSIRR_RND_SHIFT		0
2194#define	PMSIRR_RND			(UL(0x1) << PMSIRR_RND_SHIFT)
2195#define	PMSIRR_INTERVAL_SHIFT		8
2196#define	PMSIRR_INTERVAL_MASK		(UL(0xffffff) << PMSIRR_INTERVAL_SHIFT)
2197
2198/* PMSLATFR_EL1 */
2199#define	PMSLATFR_EL1			MRS_REG(PMSLATFR_EL1)
2200#define	PMSLATFR_EL1_REG		MRS_REG_ALT_NAME(PMSLATFR_EL1)
2201#define	PMSLATFR_EL1_op0		3
2202#define	PMSLATFR_EL1_op1		0
2203#define	PMSLATFR_EL1_CRn		9
2204#define	PMSLATFR_EL1_CRm		9
2205#define	PMSLATFR_EL1_op2		6
2206#define	PMSLATFR_MINLAT_SHIFT		0
2207#define	PMSLATFR_MINLAT_MASK		(UL(0xfff) << PMSLATFR_MINLAT_SHIFT)
2208
2209/* PMSNEVFR_EL1 */
2210#define	PMSNEVFR_EL1			MRS_REG(PMSNEVFR_EL1)
2211#define	PMSNEVFR_EL1_REG		MRS_REG_ALT_NAME(PMSNEVFR_EL1)
2212#define	PMSNEVFR_EL1_op0		3
2213#define	PMSNEVFR_EL1_op1		0
2214#define	PMSNEVFR_EL1_CRn		9
2215#define	PMSNEVFR_EL1_CRm		9
2216#define	PMSNEVFR_EL1_op2		1
2217
2218/* PMSWINC_EL0 */
2219#define	PMSWINC_EL0			MRS_REG(PMSWINC_EL0)
2220#define	PMSWINC_EL0_op0			3
2221#define	PMSWINC_EL0_op1			3
2222#define	PMSWINC_EL0_CRn			9
2223#define	PMSWINC_EL0_CRm			12
2224#define	PMSWINC_EL0_op2			4
2225
2226/* PMUSERENR_EL0 */
2227#define	PMUSERENR_EL0			MRS_REG(PMUSERENR_EL0)
2228#define	PMUSERENR_EL0_op0		3
2229#define	PMUSERENR_EL0_op1		3
2230#define	PMUSERENR_EL0_CRn		9
2231#define	PMUSERENR_EL0_CRm		14
2232#define	PMUSERENR_EL0_op2		0
2233
2234/* PMXEVCNTR_EL0 */
2235#define	PMXEVCNTR_EL0			MRS_REG(PMXEVCNTR_EL0)
2236#define	PMXEVCNTR_EL0_op0		3
2237#define	PMXEVCNTR_EL0_op1		3
2238#define	PMXEVCNTR_EL0_CRn		9
2239#define	PMXEVCNTR_EL0_CRm		13
2240#define	PMXEVCNTR_EL0_op2		2
2241
2242/* PMXEVTYPER_EL0 */
2243#define	PMXEVTYPER_EL0			MRS_REG(PMXEVTYPER_EL0)
2244#define	PMXEVTYPER_EL0_op0		3
2245#define	PMXEVTYPER_EL0_op1		3
2246#define	PMXEVTYPER_EL0_CRn		9
2247#define	PMXEVTYPER_EL0_CRm		13
2248#define	PMXEVTYPER_EL0_op2		1
2249
2250/* RNDRRS */
2251#define	RNDRRS				MRS_REG(RNDRRS)
2252#define	RNDRRS_REG			MRS_REG_ALT_NAME(RNDRRS)
2253#define	RNDRRS_op0			3
2254#define	RNDRRS_op1			3
2255#define	RNDRRS_CRn			2
2256#define	RNDRRS_CRm			4
2257#define	RNDRRS_op2			1
2258
2259/* SCTLR_EL1 - System Control Register */
2260#define	SCTLR_EL1_REG			MRS_REG_ALT_NAME(SCTLR_EL1)
2261#define	SCTLR_EL1_op0			3
2262#define	SCTLR_EL1_op1			0
2263#define	SCTLR_EL1_CRn			1
2264#define	SCTLR_EL1_CRm			0
2265#define	SCTLR_EL1_op2			0
2266#define	SCTLR_RES1	0x30d00800	/* Reserved ARMv8.0, write 1 */
2267#define	SCTLR_M				(UL(0x1) << 0)
2268#define	SCTLR_A				(UL(0x1) << 1)
2269#define	SCTLR_C				(UL(0x1) << 2)
2270#define	SCTLR_SA			(UL(0x1) << 3)
2271#define	SCTLR_SA0			(UL(0x1) << 4)
2272#define	SCTLR_CP15BEN			(UL(0x1) << 5)
2273#define	SCTLR_nAA			(UL(0x1) << 6)
2274#define	SCTLR_ITD			(UL(0x1) << 7)
2275#define	SCTLR_SED			(UL(0x1) << 8)
2276#define	SCTLR_UMA			(UL(0x1) << 9)
2277#define	SCTLR_EnRCTX			(UL(0x1) << 10)
2278#define	SCTLR_EOS			(UL(0x1) << 11)
2279#define	SCTLR_I				(UL(0x1) << 12)
2280#define	SCTLR_EnDB			(UL(0x1) << 13)
2281#define	SCTLR_DZE			(UL(0x1) << 14)
2282#define	SCTLR_UCT			(UL(0x1) << 15)
2283#define	SCTLR_nTWI			(UL(0x1) << 16)
2284/* Bit 17 is reserved */
2285#define	SCTLR_nTWE			(UL(0x1) << 18)
2286#define	SCTLR_WXN			(UL(0x1) << 19)
2287#define	SCTLR_TSCXT			(UL(0x1) << 20)
2288#define	SCTLR_IESB			(UL(0x1) << 21)
2289#define	SCTLR_EIS			(UL(0x1) << 22)
2290#define	SCTLR_SPAN			(UL(0x1) << 23)
2291#define	SCTLR_E0E			(UL(0x1) << 24)
2292#define	SCTLR_EE			(UL(0x1) << 25)
2293#define	SCTLR_UCI			(UL(0x1) << 26)
2294#define	SCTLR_EnDA			(UL(0x1) << 27)
2295#define	SCTLR_nTLSMD			(UL(0x1) << 28)
2296#define	SCTLR_LSMAOE			(UL(0x1) << 29)
2297#define	SCTLR_EnIB			(UL(0x1) << 30)
2298#define	SCTLR_EnIA			(UL(0x1) << 31)
2299/* Bits 34:32 are reserved */
2300#define	SCTLR_BT0			(UL(0x1) << 35)
2301#define	SCTLR_BT1			(UL(0x1) << 36)
2302#define	SCTLR_ITFSB			(UL(0x1) << 37)
2303#define	SCTLR_TCF0_MASK			(UL(0x3) << 38)
2304#define	SCTLR_TCF_MASK			(UL(0x3) << 40)
2305#define	SCTLR_ATA0			(UL(0x1) << 42)
2306#define	SCTLR_ATA			(UL(0x1) << 43)
2307#define	SCTLR_DSSBS			(UL(0x1) << 44)
2308#define	SCTLR_TWEDEn			(UL(0x1) << 45)
2309#define	SCTLR_TWEDEL_MASK		(UL(0xf) << 46)
2310/* Bits 53:50 are reserved */
2311#define	SCTLR_EnASR			(UL(0x1) << 54)
2312#define	SCTLR_EnAS0			(UL(0x1) << 55)
2313#define	SCTLR_EnALS			(UL(0x1) << 56)
2314#define	SCTLR_EPAN			(UL(0x1) << 57)
2315
2316/* SCTLR_EL12 */
2317#define	SCTLR_EL12_REG			MRS_REG_ALT_NAME(SCTLR_EL12)
2318#define	SCTLR_EL12_op0			3
2319#define	SCTLR_EL12_op1			5
2320#define	SCTLR_EL12_CRn			1
2321#define	SCTLR_EL12_CRm			0
2322#define	SCTLR_EL12_op2			0
2323
2324/* SPSR_EL1 */
2325#define	SPSR_EL1_REG			MRS_REG_ALT_NAME(SPSR_EL1)
2326#define	SPSR_EL1_op0			3
2327#define	SPSR_EL1_op1			0
2328#define	SPSR_EL1_CRn			4
2329#define	SPSR_EL1_CRm			0
2330#define	SPSR_EL1_op2			0
2331/*
2332 * When the exception is taken in AArch64:
2333 * M[3:2] is the exception level
2334 * M[1]   is unused
2335 * M[0]   is the SP select:
2336 *         0: always SP0
2337 *         1: current ELs SP
2338 */
2339#define	PSR_M_EL0t	0x00000000UL
2340#define	PSR_M_EL1t	0x00000004UL
2341#define	PSR_M_EL1h	0x00000005UL
2342#define	PSR_M_EL2t	0x00000008UL
2343#define	PSR_M_EL2h	0x00000009UL
2344#define	PSR_M_64	0x00000000UL
2345#define	PSR_M_32	0x00000010UL
2346#define	PSR_M_MASK	0x0000000fUL
2347
2348#define	PSR_T		0x00000020UL
2349
2350#define	PSR_AARCH32	0x00000010UL
2351#define	PSR_F		0x00000040UL
2352#define	PSR_I		0x00000080UL
2353#define	PSR_A		0x00000100UL
2354#define	PSR_D		0x00000200UL
2355#define	PSR_DAIF	(PSR_D | PSR_A | PSR_I | PSR_F)
2356/* The default DAIF mask. These bits are valid in spsr_el1 and daif */
2357#define	PSR_DAIF_DEFAULT (PSR_F)
2358#define	PSR_BTYPE	0x00000c00UL
2359#define	PSR_SSBS	0x00001000UL
2360#define	PSR_ALLINT	0x00002000UL
2361#define	PSR_IL		0x00100000UL
2362#define	PSR_SS		0x00200000UL
2363#define	PSR_PAN		0x00400000UL
2364#define	PSR_UAO		0x00800000UL
2365#define	PSR_DIT		0x01000000UL
2366#define	PSR_TCO		0x02000000UL
2367#define	PSR_V		0x10000000UL
2368#define	PSR_C		0x20000000UL
2369#define	PSR_Z		0x40000000UL
2370#define	PSR_N		0x80000000UL
2371#define	PSR_FLAGS	0xf0000000UL
2372/* PSR fields that can be set from 32-bit and 64-bit processes */
2373#define	PSR_SETTABLE_32	PSR_FLAGS
2374#define	PSR_SETTABLE_64	(PSR_FLAGS | PSR_SS)
2375
2376/* SPSR_EL12 */
2377#define	SPSR_EL12_REG			MRS_REG_ALT_NAME(SPSR_EL12)
2378#define	SPSR_EL12_op0			3
2379#define	SPSR_EL12_op1			5
2380#define	SPSR_EL12_CRn			4
2381#define	SPSR_EL12_CRm			0
2382#define	SPSR_EL12_op2			0
2383
2384/* REVIDR_EL1 - Revision ID Register */
2385#define	REVIDR_EL1			MRS_REG(REVIDR_EL1)
2386#define	REVIDR_EL1_op0			3
2387#define	REVIDR_EL1_op1			0
2388#define	REVIDR_EL1_CRn			0
2389#define	REVIDR_EL1_CRm			0
2390#define	REVIDR_EL1_op2			6
2391
2392/* TCR_EL1 - Translation Control Register */
2393#define	TCR_EL1_REG			MRS_REG_ALT_NAME(TCR_EL1)
2394#define	TCR_EL1_op0			3
2395#define	TCR_EL1_op1			0
2396#define	TCR_EL1_CRn			2
2397#define	TCR_EL1_CRm			0
2398#define	TCR_EL1_op2			2
2399/* Bits 63:59 are reserved */
2400#define	TCR_DS_SHIFT		59
2401#define	TCR_DS			(UL(1) << TCR_DS_SHIFT)
2402#define	TCR_TCMA1_SHIFT		58
2403#define	TCR_TCMA1		(UL(1) << TCR_TCMA1_SHIFT)
2404#define	TCR_TCMA0_SHIFT		57
2405#define	TCR_TCMA0		(UL(1) << TCR_TCMA0_SHIFT)
2406#define	TCR_E0PD1_SHIFT		56
2407#define	TCR_E0PD1		(UL(1) << TCR_E0PD1_SHIFT)
2408#define	TCR_E0PD0_SHIFT		55
2409#define	TCR_E0PD0		(UL(1) << TCR_E0PD0_SHIFT)
2410#define	TCR_NFD1_SHIFT		54
2411#define	TCR_NFD1		(UL(1) << TCR_NFD1_SHIFT)
2412#define	TCR_NFD0_SHIFT		53
2413#define	TCR_NFD0		(UL(1) << TCR_NFD0_SHIFT)
2414#define	TCR_TBID1_SHIFT		52
2415#define	TCR_TBID1		(UL(1) << TCR_TBID1_SHIFT)
2416#define	TCR_TBID0_SHIFT		51
2417#define	TCR_TBID0		(UL(1) << TCR_TBID0_SHIFT)
2418#define	TCR_HWU162_SHIFT	50
2419#define	TCR_HWU162		(UL(1) << TCR_HWU162_SHIFT)
2420#define	TCR_HWU161_SHIFT	49
2421#define	TCR_HWU161		(UL(1) << TCR_HWU161_SHIFT)
2422#define	TCR_HWU160_SHIFT	48
2423#define	TCR_HWU160		(UL(1) << TCR_HWU160_SHIFT)
2424#define	TCR_HWU159_SHIFT	47
2425#define	TCR_HWU159		(UL(1) << TCR_HWU159_SHIFT)
2426#define	TCR_HWU1		\
2427    (TCR_HWU159 | TCR_HWU160 | TCR_HWU161 | TCR_HWU162)
2428#define	TCR_HWU062_SHIFT	46
2429#define	TCR_HWU062		(UL(1) << TCR_HWU062_SHIFT)
2430#define	TCR_HWU061_SHIFT	45
2431#define	TCR_HWU061		(UL(1) << TCR_HWU061_SHIFT)
2432#define	TCR_HWU060_SHIFT	44
2433#define	TCR_HWU060		(UL(1) << TCR_HWU060_SHIFT)
2434#define	TCR_HWU059_SHIFT	43
2435#define	TCR_HWU059		(UL(1) << TCR_HWU059_SHIFT)
2436#define	TCR_HWU0		\
2437    (TCR_HWU059 | TCR_HWU060 | TCR_HWU061 | TCR_HWU062)
2438#define	TCR_HPD1_SHIFT		42
2439#define	TCR_HPD1		(UL(1) << TCR_HPD1_SHIFT)
2440#define	TCR_HPD0_SHIFT		41
2441#define	TCR_HPD0		(UL(1) << TCR_HPD0_SHIFT)
2442#define	TCR_HD_SHIFT		40
2443#define	TCR_HD			(UL(1) << TCR_HD_SHIFT)
2444#define	TCR_HA_SHIFT		39
2445#define	TCR_HA			(UL(1) << TCR_HA_SHIFT)
2446#define	TCR_TBI1_SHIFT		38
2447#define	TCR_TBI1		(UL(1) << TCR_TBI1_SHIFT)
2448#define	TCR_TBI0_SHIFT		37
2449#define	TCR_TBI0		(UL(1) << TCR_TBI0_SHIFT)
2450#define	TCR_ASID_SHIFT		36
2451#define	TCR_ASID_WIDTH		1
2452#define	TCR_ASID_16		(UL(1) << TCR_ASID_SHIFT)
2453/* Bit 35 is reserved */
2454#define	TCR_IPS_SHIFT		32
2455#define	TCR_IPS_WIDTH		3
2456#define	TCR_IPS_32BIT		(UL(0) << TCR_IPS_SHIFT)
2457#define	TCR_IPS_36BIT		(UL(1) << TCR_IPS_SHIFT)
2458#define	TCR_IPS_40BIT		(UL(2) << TCR_IPS_SHIFT)
2459#define	TCR_IPS_42BIT		(UL(3) << TCR_IPS_SHIFT)
2460#define	TCR_IPS_44BIT		(UL(4) << TCR_IPS_SHIFT)
2461#define	TCR_IPS_48BIT		(UL(5) << TCR_IPS_SHIFT)
2462#define	TCR_TG1_SHIFT		30
2463#define	TCR_TG1_MASK		(UL(3) << TCR_TG1_SHIFT)
2464#define	TCR_TG1_16K		(UL(1) << TCR_TG1_SHIFT)
2465#define	TCR_TG1_4K		(UL(2) << TCR_TG1_SHIFT)
2466#define	TCR_TG1_64K		(UL(3) << TCR_TG1_SHIFT)
2467#define	TCR_SH1_SHIFT		28
2468#define	TCR_SH1_IS		(UL(3) << TCR_SH1_SHIFT)
2469#define	TCR_ORGN1_SHIFT		26
2470#define	TCR_ORGN1_WBWA		(UL(1) << TCR_ORGN1_SHIFT)
2471#define	TCR_IRGN1_SHIFT		24
2472#define	TCR_IRGN1_WBWA		(UL(1) << TCR_IRGN1_SHIFT)
2473#define	TCR_EPD1_SHIFT		23
2474#define	TCR_EPD1		(UL(1) << TCR_EPD1_SHIFT)
2475#define	TCR_A1_SHIFT		22
2476#define	TCR_A1			(UL(1) << TCR_A1_SHIFT)
2477#define	TCR_T1SZ_SHIFT		16
2478#define	TCR_T1SZ_MASK		(UL(0x3f) << TCR_T1SZ_SHIFT)
2479#define	TCR_T1SZ(x)		((x) << TCR_T1SZ_SHIFT)
2480#define	TCR_TG0_SHIFT		14
2481#define	TCR_TG0_MASK		(UL(3) << TCR_TG0_SHIFT)
2482#define	TCR_TG0_4K		(UL(0) << TCR_TG0_SHIFT)
2483#define	TCR_TG0_64K		(UL(1) << TCR_TG0_SHIFT)
2484#define	TCR_TG0_16K		(UL(2) << TCR_TG0_SHIFT)
2485#define	TCR_SH0_SHIFT		12
2486#define	TCR_SH0_IS		(UL(3) << TCR_SH0_SHIFT)
2487#define	TCR_ORGN0_SHIFT		10
2488#define	TCR_ORGN0_WBWA		(UL(1) << TCR_ORGN0_SHIFT)
2489#define	TCR_IRGN0_SHIFT		8
2490#define	TCR_IRGN0_WBWA		(UL(1) << TCR_IRGN0_SHIFT)
2491#define	TCR_EPD0_SHIFT		7
2492#define	TCR_EPD0		(UL(1) << TCR_EPD0_SHIFT)
2493/* Bit 6 is reserved */
2494#define	TCR_T0SZ_SHIFT		0
2495#define	TCR_T0SZ_MASK		(UL(0x3f) << TCR_T0SZ_SHIFT)
2496#define	TCR_T0SZ(x)		((x) << TCR_T0SZ_SHIFT)
2497#define	TCR_TxSZ(x)		(TCR_T1SZ(x) | TCR_T0SZ(x))
2498
2499#define	TCR_CACHE_ATTRS	((TCR_IRGN0_WBWA | TCR_IRGN1_WBWA) |\
2500				(TCR_ORGN0_WBWA | TCR_ORGN1_WBWA))
2501#ifdef SMP
2502#define	TCR_SMP_ATTRS	(TCR_SH0_IS | TCR_SH1_IS)
2503#else
2504#define	TCR_SMP_ATTRS	0
2505#endif
2506
2507/* TCR_EL12 */
2508#define	TCR_EL12_REG			MRS_REG_ALT_NAME(TCR_EL12)
2509#define	TCR_EL12_op0			3
2510#define	TCR_EL12_op1			5
2511#define	TCR_EL12_CRn			2
2512#define	TCR_EL12_CRm			0
2513#define	TCR_EL12_op2			2
2514
2515/* TTBR0_EL1 & TTBR1_EL1 - Translation Table Base Register 0 & 1 */
2516#define	TTBR_ASID_SHIFT		48
2517#define	TTBR_ASID_MASK		(0xfffful << TTBR_ASID_SHIFT)
2518#define	TTBR_BADDR		0x0000fffffffffffeul
2519#define	TTBR_CnP_SHIFT		0
2520#define	TTBR_CnP		(1ul << TTBR_CnP_SHIFT)
2521
2522/* TTBR0_EL1 */
2523#define	TTBR0_EL1_REG			MRS_REG_ALT_NAME(TTBR0_EL1)
2524#define	TTBR0_EL1_op0			3
2525#define	TTBR0_EL1_op1			0
2526#define	TTBR0_EL1_CRn			2
2527#define	TTBR0_EL1_CRm			0
2528#define	TTBR0_EL1_op2			0
2529
2530/* TTBR0_EL12 */
2531#define	TTBR0_EL12_REG			MRS_REG_ALT_NAME(TTBR0_EL12)
2532#define	TTBR0_EL12_op0			3
2533#define	TTBR0_EL12_op1			5
2534#define	TTBR0_EL12_CRn			2
2535#define	TTBR0_EL12_CRm			0
2536#define	TTBR0_EL12_op2			0
2537
2538/* TTBR1_EL1 */
2539#define	TTBR1_EL1_REG			MRS_REG_ALT_NAME(TTBR1_EL1)
2540#define	TTBR1_EL1_op0			3
2541#define	TTBR1_EL1_op1			0
2542#define	TTBR1_EL1_CRn			2
2543#define	TTBR1_EL1_CRm			0
2544#define	TTBR1_EL1_op2			1
2545
2546/* TTBR1_EL12 */
2547#define	TTBR1_EL12_REG			MRS_REG_ALT_NAME(TTBR1_EL12)
2548#define	TTBR1_EL12_op0			3
2549#define	TTBR1_EL12_op1			5
2550#define	TTBR1_EL12_CRn			2
2551#define	TTBR1_EL12_CRm			0
2552#define	TTBR1_EL12_op2			1
2553
2554/* VBAR_EL1 */
2555#define	VBAR_EL1_REG			MRS_REG_ALT_NAME(VBAR_EL1)
2556#define	VBAR_EL1_op0			3
2557#define	VBAR_EL1_op1			0
2558#define	VBAR_EL1_CRn			12
2559#define	VBAR_EL1_CRm			0
2560#define	VBAR_EL1_op2			0
2561
2562/* VBAR_EL12 */
2563#define	VBAR_EL12_REG			MRS_REG_ALT_NAME(VBAR_EL12)
2564#define	VBAR_EL12_op0			3
2565#define	VBAR_EL12_op1			5
2566#define	VBAR_EL12_CRn			12
2567#define	VBAR_EL12_CRm			0
2568#define	VBAR_EL12_op2			0
2569
2570/* ZCR_EL1 - SVE Control Register */
2571#define	ZCR_EL1			MRS_REG(ZCR_EL1)
2572#define	ZCR_EL1_REG		MRS_REG_ALT_NAME(ZCR_EL1_REG)
2573#define	ZCR_EL1_REG_op0		3
2574#define	ZCR_EL1_REG_op1		0
2575#define	ZCR_EL1_REG_CRn		1
2576#define	ZCR_EL1_REG_CRm		2
2577#define	ZCR_EL1_REG_op2		0
2578#define	ZCR_LEN_SHIFT		0
2579#define	ZCR_LEN_MASK		(0xf << ZCR_LEN_SHIFT)
2580#define	ZCR_LEN_BYTES(x)	((((x) & ZCR_LEN_MASK) + 1) * 16)
2581
2582#endif /* !_MACHINE_ARMREG_H_ */
2583
2584#endif /* !__arm__ */