1/*-
  2 * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com>
  3 * Copyright 2014 Michal Meloun <meloun@miracle.cz>
  4 * All rights reserved.
  5 *
  6 * Redistribution and use in source and binary forms, with or without
  7 * modification, are permitted provided that the following conditions
  8 * are met:
  9 * 1. Redistributions of source code must retain the above copyright
 10 *    notice, this list of conditions and the following disclaimer.
 11 * 2. Redistributions in binary form must reproduce the above copyright
 12 *    notice, this list of conditions and the following disclaimer in the
 13 *    documentation and/or other materials provided with the distribution.
 14 *
 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 18 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 25 * SUCH DAMAGE.
 26 */
 27
 28#ifndef	_MACHINE_CPUINFO_H_
 29#define	_MACHINE_CPUINFO_H_
 30
 31#include <sys/types.h>
 32
 33#define CPU_IMPLEMENTER_ARM		0x41
 34#define CPU_IMPLEMENTER_QCOM		0x51
 35#define CPU_IMPLEMENTER_MRVL		0x56
 36
 37/* ARM */
 38#define CPU_ARCH_ARM1176		0xB76
 39#define CPU_ARCH_CORTEX_A5		0xC05
 40#define CPU_ARCH_CORTEX_A7		0xC07
 41#define CPU_ARCH_CORTEX_A8		0xC08
 42#define CPU_ARCH_CORTEX_A9		0xC09
 43#define CPU_ARCH_CORTEX_A12		0xC0D
 44#define CPU_ARCH_CORTEX_A15		0xC0F
 45#define CPU_ARCH_CORTEX_A17		0xC11
 46#define CPU_ARCH_CORTEX_A53		0xD03
 47#define CPU_ARCH_CORTEX_A57		0xD07
 48#define CPU_ARCH_CORTEX_A72		0xD08
 49#define CPU_ARCH_CORTEX_A73		0xD09
 50#define CPU_ARCH_CORTEX_A75		0xD0A
 51
 52/* QCOM */
 53#define CPU_ARCH_KRAIT_300		0x06F
 54
 55/* MRVL */
 56#define CPU_ARCH_SHEEVA_581		0x581	/* PJ4/PJ4B */
 57#define CPU_ARCH_SHEEVA_584		0x584 	/* PJ4B-MP/PJ4C */
 58
 59struct cpuinfo {
 60	/* raw id registers */
 61	uint32_t midr;
 62	uint32_t ctr;
 63	uint32_t tcmtr;
 64	uint32_t tlbtr;
 65	uint32_t mpidr;
 66	uint32_t revidr;
 67	uint32_t id_pfr0;
 68	uint32_t id_pfr1;
 69	uint32_t id_dfr0;
 70	uint32_t id_afr0;
 71	uint32_t id_mmfr0;
 72	uint32_t id_mmfr1;
 73	uint32_t id_mmfr2;
 74	uint32_t id_mmfr3;
 75	uint32_t id_isar0;
 76	uint32_t id_isar1;
 77	uint32_t id_isar2;
 78	uint32_t id_isar3;
 79	uint32_t id_isar4;
 80	uint32_t id_isar5;
 81	uint32_t cbar;
 82	uint32_t ccsidr;
 83	uint32_t clidr;
 84
 85	/* Parsed bits of above registers... */
 86
 87	/* midr */
 88	int implementer;
 89	int revision;
 90	int architecture;
 91	int part_number;
 92	int patch;
 93
 94	/* id_mmfr0 */
 95	int outermost_shareability;
 96	int shareability_levels;
 97	int auxiliary_registers;
 98	int innermost_shareability;
 99
100	/* id_mmfr1 */
101	int mem_barrier;
102
103	/* id_mmfr3 */
104	int coherent_walk;
105	int maintenance_broadcast;
106
107	/* id_pfr1 */
108	int generic_timer_ext;
109	int virtualization_ext;
110	int security_ext;
111
112	/* L1 cache info */
113	int dcache_line_size;
114	int dcache_line_mask;
115	int icache_line_size;
116	int icache_line_mask;
117
118	/* mpidr */
119	int mp_ext;
120};
121
122extern struct cpuinfo cpuinfo;
123
124void cpuinfo_init(void);
125void cpuinfo_init_bp_hardening(void);
126void cpuinfo_reinit_mmu(uint32_t ttb);
127#endif	/* _MACHINE_CPUINFO_H_ */